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s3c9432/c9434/p9434 product overview 1 - 1 1 product overview sam87r i product family samsung's sam87ri family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. a address/data bus architecture and a large number of bit- configurable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counters with selectable operating modes are included to support real-time operations. s3c9432/c9434 microcontroller the s3c9432/c9434 single-chip 8-bit microcontroller is fabricated using an advanced cmos process. it is built around the powerful sam87ri cpu core. the s3c9432/c9434 is a versatile microcontroller , with its a/d converter, timer, pwm, and sio it can be used in a wide range of general purpose applications. stop and idle power-down modes were implemented to reduce power consumption. to increase on-chip register space, the size of the internal register file was logically expanded. the s3c9432/c9434 ha ve 2k-bytes or 4 k- byte s of program memory on-chip (rom) and 112-bytes of general purpose register area ram . using the sam87ri design approach, the following peripherals were integrated with the sam87ri core: ? three configurable i/o ports (13 pins) ? five interrupt s ources with one vector and one interrupt level ? one 8-bit timer/counter with time interval mode ? analog to digital converter with five input channels and 10-bit resolution ? one synchronous sio module ? one 12-bit pwm output the s3c9432/c9434 microcontroller is ideal for use in a wide range of electronic applications requiring simple timer/counter, pwm, adc, and sio. s3c9432/c9434 is available in a 20/18/16- pin dip and a 20-pin sop package. otp the S3P9434 is an otp (one time programmable) version of the s3c9432/c9434 microcontroller. the S3P9434 has on-chip 4k-byte one-time-programmable eprom instead of masked rom. the S3P9434 is fully compatible with the s3c9432/c9434, in function, in d.c. electrical characteristics and in pin configuration.
product overview s3c9432/c9434/p943 4 1 - 2 features cpu ? sam87r i cpu core memory ? 2/ 4 k-byte internal program memory (rom) ? 112 -byte general purpose register area (ram) instruction set ? 41 instructions ? the sam87ri core provides all the sam87 core instruction except the word-oriented instruction, multiplication, division, and some one-byte instruction. instruction execution time ? 600 n s at 10 mhz f osc (minimum cycles) ? 375 n s at 16 mhz f osc (minimum cycles) interrupts ? 5 interrupt sources with one vector and o ne level interrupt structure general i/o ? two i/o ports (toatal 13 pins ) ? one output only port (port 2) ? bit programmable ports serial i/o ? one synchronius serial i/o module ? selectable transmit and receive rates built-in reset circuit (lvd) ? low voltage detector for safe reset timer/counter s ? one 8-bit ba sic timer for watchdog function ? one 8- bit timer/counter for the time interval mode pwm module ? 12-bit pwm 1-ch (max: 250 khz) ? 6-bit base + 6-bit extension frame a/d converter ? five analog input pins ? 10-bit conversion resolution buzzer frequency range ? 200 hz to 20 khz signal can be generated oscillation frequency ? 1 mhz to 16 mhz external crystal oscillator ? maximum 16 mhz cpu clock ? 4 mhz rc oscillator operating temperature range ? - 4 0 c to + 85 c operating voltage range ? 3.0 v to 5.5 v otp interface protocol spec ? serial otp package types ? 2 0-pin dip -300 ? 20-pin sop-375 ? 18-pin dip-300 ? 16-pin dip-300
s3c9432/c9434/p9434 product overview 1 - 3 block diagram sam87ri cpu p0.0-p0.3 buz, pwm, int0, int1 i/o port and interrupt control 2-kb rom 4-kb rom 112-byte register file port 0 port 1 p1.0-p1.4 adc0-adc4 sck, so, si, clo port 2 sio timer 0 buz adc pwm osc basic timer p2.0/sck p2.1/so p2.2 p2.3 sck (p1.3 or p2.0) so (p1.2 or p2.1) si (p1.1) x in x out p0.2/t0ck p0.0/buz adc0-adc4 p0.1/pwm figure 1 -1 . block diagram
product overview s3c9432/c9434/p943 4 1 - 4 pin assignments s3c9432/c9434 20-dip (top view) v dd p0.3/int1 (scl) p1.0/adc0 (sda) p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/cl0 av ref p2.1/so p2.3 20 19 18 17 16 15 14 13 12 11 v ss x in x out test (v pp ) p0.2/t0ck/int0 p0.1/pwm reset p0.0/buz p2.0/sck p2.2 1 2 3 4 5 6 7 8 9 10 figure 1 -2 . pin assignment diagram ( 20 -pin dip package)
s3c9432/c9434/p9434 product overview 1 - 5 s3c9432/c9434 20-sop (top view) v dd p0.3/int1 p1.0/adc0 p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/clo av ref p2.1/so p2.3 20 19 18 17 16 15 14 13 12 11 v ss x in x out test p0.2/t0ck/int0 p0.1/pwm reset p0.0/buz p2.0/sck p2.2 1 2 3 4 5 6 7 8 9 10 figure 1 -3 . pin assignment diagram ( 20 -pin sop package)
product overview s3c9432/c9434/p943 4 1 - 6 s3c9432/c9434 18-dip (top view) v dd p0.3/int1 p1.0/adc0 p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/cl0 av ref p2.1/so 18 17 16 15 14 13 12 11 10 v ss x in x out test p0.2/t0ck/int0 p0.1/pwm reset p0.0/buz p2.0/sck 1 2 3 4 5 6 7 8 9 figure 1 -4 . pin assignment diagram ( 18 -pin dip package) s3c9432/c9434 16-dip (top view) v ss x in x out test p0.2/t0ck/int0 p0.1/pwm reset p0.0/buz v dd p0.3/int1 p1.0/adc0 p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/clo av ref 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 figure 1-5. pin assignment diagram (16-pin dip package)
s3c9432/c9434/p9434 product overview 1 - 7 pin descriptions table 1 - 1. s3c9432/c9434 pin descriptions pin names pin type pin description circuit type share pins p0.0-p0. 3 i/o bit-programmable i/o port for schmitt trigger input or push-pull, open-drain output. pull-up resistors are assignable by software. port 0 pins can also be used as alternative function. e buz pwm int0/t0ck int1 p1.0-p1.4 i/o bit-programmable i/o port for schmitt trigger input or push-pull , open-drain output. pull-up resistors are assignable by software. port 1 pins can also be used as alternative function. e-1 adc0-adc4 si so sck clo p2.0-p2.3 o p ush-pull or open-drain output port. pull up resistors are assignable by software. port 2 .0-2.1 pins can also be used as alternative function. e-2 sck so x in , x out ? crystal/ceramic, or rc oscillator signal for system clock. ? ? reset i system reset signal input pin. b ? test i test signal input pin (for factory use only: must be connected to v ss ) ? ? v dd , v ss ? voltage input pin and ground ? ? av ref ? a/d converter reference voltage input and ground ? ? a v ss bonded to v ss internally sck i/o serial interface clock i/o e-1 e-2 p1.3 or p2.0 so o serial data output e-1 e-2 p1.2 or p2.1 si i serial data input e-1 p1.1 clo o system clock output port e-1 p1.4 buz o 200 hz- 20 khz frequency output for buzzer sound e p0.0 pwm o 12-bit pwm output e p0.1 int 0-int1 i external interrupt input port e p0.2 p0.3 t0ck i timer 0 external clock input e p0.2 adc0-adc4 i a/d converter input e-1 p1.0-p1.4
product overview s3c9432/c9434/p943 4 1 - 8 pin circuits p-channel n-channel in v dd figure 1 -6 . pin circuit type a in v dd pull-up resistor figure 1 -7 . pin circuit type b p-channel n-channel v dd out output disable data figure 1 -8 . pin circuit type c i/o output disable data circuit type c pull-up enable v dd data p-channel figure 1 -9 . pin circuit typ e d
s3c9432/c9434/p9434 product overview 1 - 9 n-ch v dd p-ch output disable output data open-drain input pull-up enable v dd i/o pull-up resistor figure 1 -10 . pin circuit type e analog input n-ch v dd p-ch output disable output data open-drain digital input pull-up enable v dd i/o pull-up resistor figure 1 -11 . pin circuit type e-1 n-ch v dd p-ch output disable output data open-drain pull-up enable v dd i/o pull-up resistor figure 1 -12 . pin circuit type e-2
s3c9432/c9434/p9434 address spaces 2 - 1 2 address spaces overview the s3c9432/c9434 microcontroller has two kinds of address space: ? internal p rogram memory (rom ) ? internal register file a 12 -bit address bus supports program memory operations. a separate 8 -bit register bus carries addresses and data between the cpu and the internal register file. the s3c9432/c9434 have 2k-bytes or 4k-bytes of mask-progr ammable on-chip program memory: which is configured as the internal rom mode, all of the 4-kbyte internal program memory is used. the s3c9432/c9434 microcontroller has 112 general-purpose registers in its internal register file. thirty-one bytes in the register file are mapped for system and peripheral control functions.
address spaces s3c9432/c9434/p9434 2 - 2 program memory (rom) normal operating mode the s3c9432/c9434 ha ve 2k-bytes (locations 0h - 0 7 ffh) or 4k-bytes (locations 0h-0fffh) of internal mask- programmable program memory. the first 2 - bytes of the rom (0000h -0001h) are interrupt vector address. unused locations (0002h-00ffh) can be used as normal program memory. the program reset address in the rom is 0100h. (decimal) 4.095 256 0 4k-byte program memory area interrupt vector 1 2 program start 2k-byte program memory area 2,047 (hex) 0fffh 0100h 0000h 0002h 0001h 07ffh figure 2 - 1. program memory address space
s3c9432/c9434/p9434 address spaces 2 - 3 register architecture the upper 64 - bytes of the s3c9432/c9434 's internal register file are addressed as working registers, system cont rol regi ste r s and periphe r al control registers. the lower 9 6- bytes of internal register file(00h -5 fh) is called the general purpose register space . the total addressable registe r space is thereby 160-bytes. 143 registers in this space can be accesse d; 112 are available for gener al-purpose use. for many sam87ri microcontrollers, the addressable area of the internal register file is further expanded by additional register pages at the general purpose register space (00h - bfh : page0) . this register file expansion is not implemented in the s3c9432/c9434 , however. the specific register types and the area (in bytes) that they occupy in the internal register file are summarized in table 2 - 1. table 2 - 1. register type summary register type number of bytes cpu and system control registers 11 peripheral, i/o, and clock control and data registers 20 general-purpose registers (including the 16-bit common working register area) 112 total addressable bytes 143
address spaces s3c9432/c9434/p9434 2 - 4 ffh c0h ~ bfh 00h 192 bytes (page 0) 64 bytes of common area 5fh d0h cfh e0h dfh not mapped general purpose register file and stack area working registers system control registers peripheral control registers figure 2 - 2. internal register file organization
s3c9432/c9434/p9434 address spaces 2 - 5 common working register area (c0h - cfh) the sam87r i register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. this16-byte address range is called common area. that is, locations in this area can be used as working registers by operations that address any location on any page in the register file. typically, these working registers serve as temporary buffers for data operations between different pages. however, because the s3c9432/c9434 uses only page 0, you can use the common area for any internal data operation. the register (r) addressing mode can be used to access this area registers are addressed either as a single 8-bit register or as a paired 16-bit register. in 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. msb rn lsb rn+1 n = even address figure 2 - 3. 16-bit register pairs + + programming tip ? addressing the common working register area as the following examples show, you should access working registers in the common area, locations c0h?cfh, using working register addressing mode only. example s : 1 . ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: ld r2,40h ; r2 (c2h) ? the value in location 40h 2 . add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: add r3,#45h ; r3 (c3h) ? r3 + 45h
address spaces s3c9432/c9434/p9434 2 - 6 system stack s3c9 -series microcontrollers use the system stack for subroutine calls and returns and to store data. the push and pop instructions are used to control system stack operations. the s3c9432/c9434 architecture supports stack operations in the internal register file. stack operations return addresses for procedure calls and interrupts and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by the ret instruction. when an interrupt occurs, the contents of the pc and the flags register are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address is always decremented before a push operation and incremented after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2 -4 . stack contects after a call instruction stack contects after an interrupt top of stack flags pch pcl pcl pch top of stack low address high address figure 2 - 4. stack operations stack pointer (sp) register location d9h contains the 8-bit stack pointer (sp) that is used for system stack operations. after a reset, the sp value is undetermined. because only internal memory space is implemented in the s3c9432/c9434 , the sp must be initialized to an 8- bit value in the range 00h? 060h . note in case a stack pointer is initialized to 00h, it is decre as ed to ffh when stack operation starts. this means that a stack pointer access invalid stack area.
s3c9432/c9434/p9434 address spaces 2 - 7 + programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operations in the internal register file using push and pop instructions: ld sp,#60 h ; sp ? 60 h (normally, the sp is set to 60 h by the ; initialization routine) ? ? ? push sym ; stack address 0bfh ? sym push r15 ; stack address 0be h ? r15 push 20h ; stack address 0bdh ? 20h push r3 ; stack address 0bch ? r3 ? ? ? pop r3 ; r3 ? stack address 0bch pop 20h ; 20h ? stack address 0bdh pop r15 ; r15 ? stack address 0beh pop sym ; sym ? stack address 0bfh
s3c9432/c9434/p9434 addressing modes 3 - 1 3 addressing modes overview instructions that are stored in program memory are fetched for execution using the program counter. instructions indicate the operation to be performed and the data to be operated on. addressing mode is the method used to determine the location of the data operand. the operands specified in sam87ri instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the sam87ri instruction set supports six explicit addressing modes. not all of these addressing modes are available for each instruction. the addressing modes and their symbols are as follows: ? register (r) ? indirect register (ir) ? indexed (x) ? direct address (da) ? relative address (ra) ? immediate (im)
addressing modes s3c9432/c9434/p9434 3 - 2 register addressing mode (r) in register addressing mode, the operand is the content of a specified register (see figure 3 - 1). working register addressing differs from register addressing because it uses an 16 -byte working register space in the register file and an 4-bit register within that space (see figure 3 - 2). dst value used in instruction execution opcode operand 8-bit register file address point to one rigister in register file one-operand instruction (example) sample instruction: dec cntr ; where cntr is the label of an 8-bit register address program memory register file figure 3 - 1. register addressing 4-bit working register point to the woking register (1 of 8) two-operand instruction (example) sample instruction: add r1, r2 ; where r1 and r2 are registers in the curruntly selected working register area. program memory register file 3 lsbs rp0 or rp1 selected rp points to start of working register block msb point to rp0 ot rp1 dst opcode src operand figure 3 - 2. working register addressing
s3c9432/c9434/p9434 addressing modes 3 - 3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space (see figures 3 - 3 through 3 - 6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. dst address of operand used by instruction opcode address 8-bit register file address point to one rigister in register file one-operand instruction (example) sample instruction: rl @shift ; where shift is the label of an 8-bit register address program memory register file value used in instruction execution operand figure 3 - 3. indirect register addressing to register file
addressing modes s3c9432/c9434/p9434 3 - 4 indirect register addressing mode (c ontinued ) pair points to rigister pair example instruction references program memory sample instructions: call @rr2 jp @rr2 register file value used in instruction register 16-bit address points to program memory operand program memory opcode program memory dst figure 3 - 4. indirect register addressing to program memory
s3c9432/c9434/p9434 addressing modes 3 - 5 indirect register addressing mode (c ontinued ) dst opcode operand 4-bit working register address points to the working register (1 of 16) sample instruction: or r6, @r2 program memory register file src 4 lsbs value used in instruction operand cfh c0h . . . . figure 3 - 5. indirect working register addressing to register file
addressing modes s3c9432/c9434/p9434 3 - 6 indirect register addressing mode (c oncluded ) dst opcode 4-bit working register address sample instructions: ldc r5,@rr6 ; program memory access lde r3,@rr14 ; external data memory access lde @rr4, r8 ; external data memory access program memory register file src value used in instruction operand example instruction references either program memory or data memory program memory or data memory next 3 bits point to working register pair (1 of 8) lsb selects register pair 16-bit address points to program memory or data memory cfh . . . . c0h figure 3 - 6. indirect working register addressing to program or data memory
s3c9432/c9434/p9434 addressing modes 3 - 7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see figure 3 - 7). you can use indexed addressing mode to access locations in the internal register file or in external memory. in short offset indexed addressing mode, the 8 -bit displacement is treated as a signed integer in the range ? 128 to + 127. this applies to external memory accesses only (see figure 3 - 8). for register file addressing, an 8 -bit base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to the base address (see figure 3 - 9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory, external program memory, and for external data memory, when implemented. dst opcode two-operand instruction example point to one of the woking register (1 of 16) sample instruction: ld r0, #base[r1] ; where base is an 8-bit immediate value program memory register file 4 lsbs value used in instruction operand index x (offset) ~ ~ ~ ~ + src figure 3 - 7. indexed addressing to register file
addressing modes s3c9432/c9434/p9434 3 - 8 indexed addressing mode (c ontinued ) point to working register pair (1 of 8) lsb selects 16-bit address added to offset dst opcode program memory xs (offset) 4-bit working register address sample instructions: ldc r4, #04h[rr2] ; the values in the program address (rr2 + #04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 3 bits register pair src 8-bits 16-bits + program memory or data memory operand value used in instruction 16-bits register file figure 3 - 8. indexed addressing to program or data memory with short offset
s3c9432/c9434/p9434 addressing modes 3 - 9 indexed addressing mode (c oncluded ) point to working register pair (1 of 8) lsb selects 16-bit address added to offset program memory 4-bit working register address sample instructions: ldc r4, #1000h[rr2] ; the values in the program address (rr2 + #1000h) are loaded into register r4. lde r4, #1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 3 bits register pair 8-bits 16-bits + program memory or data memory operand value used in instruction 16-bits register file opcode xl h (offset) xl l (offset) dst src figure 3 - 9. indexed addressing to program or data memory with long offset
addressing modes s3c9432/c9434/p9434 3 - 10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. dst/src opcode program memory "0" or "1" lower address byte lsb selects program memory or data memory: "0" = program memory "1" = data memory memory address used upper address byte program or data memory figure 3 - 10. direct addressing for load instructions
s3c9432/c9434/p9434 addressing modes 3 - 11 direct address mode (c ontinued ) opcode program memory upper address byte program memory address used lower address byte sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address next opcode figure 3 - 11. direct addressing for call and jump instructions
addressing modes s3c9432/c9434/p9434 3 - 12 relative address mode (ra) in relative address (ra) mode, a two's-complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. the instructions that support ra addressing is jr. current instruction opcode program memory displacement program memory address used sample instructions: jr ult,$+offset ; where offset is a value in the range +127 to -128 next opcode + signed displacement value current pc value figure 3 - 12. relative addressing immediate mode (im) in immediate (im) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. immediate addressing mode is useful for loading constant values into registers. (the operand value is in the instruction) sample instruction: ld r0,#0aah opcode program memory operand figure 3 - 13. immediate addressing
s3c9432/c9434/p9434 control registers 4 - 1 4 control registers overview in this section, detailed descriptions of the s3c9432/c9434 control registers are presented in an easy-to-read format. these descriptions will help familiarize you with the mapped locations in the register file. you can also use them as a quick-reference source when writing application programs. system and peripheral registers are summarized in table 4 - 1. figure 4 - 1 illustrates the important features of the standard register description format. control register descriptions are arranged in alphabetical order according to register mnemonic. more information about control registers is presented in the context of the various peripheral hardware descriptions in part ii of this manual.
control registers s3c9432/c9434/p9434 4 - 2 table 4 - 1. system and peripheral control registers register name mnemonic hex r/w timer 0 counter register t0cnt d0h r timer 0 data register t0data d1h r/w timer 0 control register t0con d2h r/w location d 3h is not mapped. clock cont r ol register clkcon d4h r/w system flags register flags d5h r/w locations d6h? d8h are not mapped. stack pointer register sp d9h r/w location dah is reserved. mds special register mdsreg dbh r/w basic timer control register btcon dch r/w basic timer counter btcnt ddh r test mode control register ftstcon deh w system mode register sym dfh r/w note: the factory test mode register, ftstcon, is for factory use only. its value should always be '00h' during the normal operation.
s3c9432/c9434/p9434 control registers 4 - 3 table 4 -1. system and peripheral c ontrol registers (continued) register name mnemonic hex r/w port 0 data register p0 e0h r/w port 1 data register p1 e1h r/w port 2 data register p2 e2h r/w locations e3h-e5h are not mapped. port 0 control register p0con e6h r/w po rt 0 open-drain & pull-up control register p0dpur e7h r/w port 0 interrupt pending register p0pnd e8h r/w po rt 1 control register (high byte) p1conh e9h r/w po rt 1 control register (low byte) p1conl e a h r/w po rt 1 open-drain & pull-up control register p1dpur e b h r/w por t 2 control register p2con e c h r/w locations edh-eeh are not mapped. sio data register siodata e f h r/w sio control register siocon f0 h r/w sio prescaler siops f1 h r/w pwm data register pwmdata f2h r/w pwm extension data register pwmex f3h r/w pwm control register pwmcon f4h r/w location f5h is not mapped. prescaler for buzzer output buzps f6h r/w a/d control register adcon f7h r/w a/d converter data register (high byte) addatah f8h r a/d converter data register (low byte) addatal f9h r locations fa h - ffh are not mapped.
control registers s3c9432/c9434/p9434 4 - 4 flags - system flags register .7 .6 .5 bit identifier reset value read/write r = read-only w = write-only r/w = read/write ' - ' = not used bit number: msb = bit 7 lsb = bit 0 addressing mode or modes you can use to modify register values description of the effect of specific bit settings reset value notation: '-' = not used 'x' = undetermind value '0' = logic zero '1' = logic one bit number(s) that is/are appended to the register name for bit addressing d5h register address (hexadecimal) full register name register mnemonic name of individual bit or bit function .7 .6 .5 .4 .2 .3 .1 .0 x r/w x r/w x r/w x r/w 0 r/w x r/w 0 r/w x r/w carry flag (c) 0 operation dose not generate a carry or borrow condition 1 operation generates carry-out or borrow into high-order bit7 zero flag 0 operation result is a non-zero value 1 operation result is zero sign flag 0 operation generates positive number (msb = "0") 1 operation generates negative number (msb = "1") figure 4 - 1. register description format
s3c9432/c9434/p9434 control registers 4 - 5 ad con ? a/d converter control register f7 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.4 a/d converter input pin selection bits 0 0 0 0 adc0 (p1.0) 0 0 0 1 adc1 (p1.1) 0 0 1 0 adc2 (p1.2) 0 0 1 1 adc3 (p1.3) 0 1 0 0 adc4 (p1.4) 0 1 0 1 internally connected with gnd internally connected with gnd 1 1 1 0 internally connected with gnd 1 1 1 1 internally connected with avref .3 end-of-conversion status bit 0 a/d conversion is in progress 1 a/d conversion complete .2-.1 clock source selection bit (note) 0 0 f osc /16 ( f osc 16 mhz) 0 1 f osc /8 ( f osc 16 mhz) 1 0 f osc /4 ( f osc 10 mhz) 1 1 f osc /1 ( f osc 2.5 mhz) .0 conversion start bit 0 no meaning 1 a/d conversion start note: maximum adc clock input = 2.5 mhz.
control registers s3c9432/c9434/p9434 4 - 6 btcon ? basic timer control register dch bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 - .4 watchdog timer function enable bit 1 0 1 0 disable watchdog timer function o ther s enable watchdog timer function .3-.2 basic timer input clock selection bits 0 0 f osc /4096 0 1 f osc /1024 1 0 f osc /128 1 1 invalid setting .1 basic timer 8-bit counter clear bit ( n ote) 0 no effect 1 clear basic timer counter value .0 basic timer divider clear bit ( n ote) 0 no effect 1 clear both dividers note: when you write a "1" to btcon.0 (or btcon.1), the basic timer divider (or b asic timer counter) is cleared. the bit is then cleared automatically to "0".
s3c9432/c9434/p9434 control registers 4 - 7 buzps ? 6-bit prescaler for buzzer output f6h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 buzzer output enable bit 0 disable buzzer output (buzzer off) 1 enable buzzer output (buzzer on) .6 buzzer clock selection bit 0 divided by 256 (fx/256) 1 divided by 64 (fx/64) .5-.0 6-bit prescaler 0 0 0 0 0 0 divided by 2 [fx/(256 or 64)] 0 0 0 0 0 1 divided by 4 [fx/(256 or 64)] 0 0 0 0 1 0 divided by 6 [fx/(256 or 64)] 0 0 0 0 1 1 divided by 8 [fx/(256 or 64)] divided by 2x(n+1) [fx/(256 or 64)] 1 1 1 1 1 1 divided by 128 [fx/(256 or 64)] note: when p0.0/buzzer is used as buzzer output pin, the initial value is 0. when the bit 7 of buzps is set to 0, the output of p0.0 is low.
control registers s3c9432/c9434/p9434 4 - 8 clkcon ? system clock control register d4h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 ? ? 0 0 ? ? ? read/write r/w ? ? r/w r/w ? ? ? .7 oscillator irq wake-up function enable bit 0 enable irq for main system oscillator wake-up function 1 disable irq for main system oscillator wake-up function .6-.5 not used for s3c9432/c9434/p9434 .4-.3 cpu clock (system clock) selection bits (1) 0 0 divide by 16 (f osc /16) 0 1 divide by 8 (f osc /8) 1 0 divide by 2 (f osc /2) 1 1 non-divided clock (f osc ) (2) .2 - .0 not used for s3c9432/c9434/p9434 notes: 1. after a reset, the slowest clock (divided by 16) is selected as the system clock. to select faster clock speeds, load the appropriate values to clkcon.3 and clkcon.4. 2. f osc means oscillator frequency
s3c9432/c9434/p9434 control registers 4 - 9 flags ? system flags register d5h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x ? ? ? ? read/write r/w r/w r/w r/w ? ? ? ? .7 carry flag (c) 0 operation does not generate a carry or borrow condition 1 operation generates a carry-out or borrow into high-order bit 7 .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is + 127 or 3 ? 128 1 operation result is > + 127 or < ? 128 .3? .0 not used for s3c9432/c9434/p9434
control registers s3c9432/c9434/p9434 4 - 10 p0con ? port 0 control register e6h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 port 0, p0.3/int1 configuration bits 0 0 schmitt trigger input; int1 interrupt disable 0 1 schmitt trigger input; interrupt on falling edge 1 0 push-pull output 1 1 schmitt trigger input; interrupt on rising edge .5-.4 port 0, p0.2/t0ck/int0 configuration bits 0 0 schmitt trigger input (t0ck input); int0 interrupt disable 0 1 schmitt trigger input (t0ck input); interrupt on falling edge 1 0 push-pull output 1 1 schmitt trigger input (t0ck input); interrupt on rising edge .3-.2 port 0, p0.1/pwm configuration bits 0 0 schmitt trigger input 0 1 schmitt trigger input 1 0 push-pull output 1 1 alternative function (pwm output) .1- .0 port 0, p0.0/buz configuration bits 0 0 schmitt trigger input 0 1 schmitt trigger input 1 0 push-pull output 1 1 alternative function (buz output)
s3c9432/c9434/p9434 control registers 4 - 11 p0dpur ? port 0 pull-up resistor enable register e7 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 port 0.3/int1 n-channel open-drain enable bit 0 configure p0.3 as a push-pull output 1 configure p0.3 as a n-channel open-drain output .6 port 0.2/t0ck/int0 n-channel open-drain enable bit 0 configure p0.2 as a push-pull output 1 configure p0.2 as a n-channel open-drain output .5 port 0.1/pwm n-channel open-drain enable bit 0 configure p0.1 as a push-pull output 1 configure p0.1 as a n-channel open-drain output .4 port 0.0/buz n-channel open-drain enable bit 0 configure p0.0 as a push-pull output 1 configure p0.0 as a n-channel open-drain output .3 port 0.3/int1 pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .2 port 0.2/t0ck/int0 pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .1 port 0.1/pwm pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .0 port 0.0/buz pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor note: in order to use the open-drain output mode, the push-pull output bit in the p0con should be set first.
control registers s3c9432/c9434/p9434 4 - 12 p 0pnd ? port 0 interrupt pending register e8h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? ? 0 0 read/write ? ? ? ? ? ? r/w r/w .7-.2 not used for the s3c9432/c9434/p9434 .1 port 0.3/int1 interrupt pending bit 0 no interrupt pending (when read) 0 pending bit clear (when write) 1 interrupt is pending (when read) 1 no effect (when write) .0 port 0.2/int0 interrupt pending bit 0 no interrupt pending (when read) 0 pending bit clear (when write) 1 interrupt is pending (when read) 1 no effect (when write) notes: 1. to clear an interrupt pending condition at a port0 pin, you must write a "0" to the corresponding p0pnd bit location. 2. to avoid programming errors, we recommend using load instructions when manipulating p0pnd values.
s3c9432/c9434/p9434 control registers 4 - 13 p1con h ? port 1 control register (high byte) e9h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? 0 0 0 read/write ? ? ? ? ? r/w r/w r/w .7-.3 not used for the s3c9432/c9434/p9434 . 2- . 0 port 1, p1.4/adc4/clo configuration bits 0 0 x schmitt trigger input 0 1 0 schmitt trigger input; pull-up enable 0 1 1 a/d converter input (adc4); schmitt trigger input off 1 0 0 push-pull output 1 0 1 open-drain output 1 1 0 open-drain output; pull-up enable 1 1 1 alternative function; clo output
control registers s3c9432/c9434/p9434 4 - 14 p 1 con l ? port 1 control register (low byte) eah bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 port 1 , p 1 . 3 / adc3/sck configuration bits 0 0 schmitt trigger input ; sck input 0 1 alternative function; sck output 1 0 push-pull output 1 1 a/d converter input (adc3); schmitt trigger input off .5-.4 port 1 , p 1 . 2 / adc2/so configuration bits 0 0 schmitt trigger input 0 1 alternative function; so output 1 0 push-pull output 1 1 a/d converter input (adc2); schmitt trigger input off .3-.2 port 1 , p 1 . 1 / adc1/si configuration bits 0 0 schmitt trigger input ; si input 0 1 schmitt trigger input ; si input 1 0 push-pull output 1 1 a/d converter input (adc1); schmitt trigger input off .1- .0 port 1 , p 1 . 0 / adc0 configuration bits 0 0 schmitt trigger input 0 1 schmitt trigger input 1 0 push-pull output 1 1 a/d converter input (adc0); schmitt trigger input off
s3c9432/c9434/p9434 control registers 4 - 15 p 1dpur ? port 1 open-drain & pull-up control register eb h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 port 1.3 n-channel open-drain enable bit 0 configure p1.3 as a push-pull output 1 configure p1.3 as a n-channel open drain output .6 port 1.2 n-channel open-drain enable bit 0 configure p1.2 as a push-pull output 1 configure p1.2 as a n-channel open drain output .5 port 1.1 n-channel open-drain enable bit 0 configure p1.1 as a push-pull output 1 configure p1.1 as a n-channel open drain output .4 port 1.0 n-channel open-drain enable bit 0 configure p1.0 as a push-pull output 1 configure p1.0 as a n-channel open drain output .3 port 1.3 pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .2 port 1.2 pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .1 port 1.1 pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor .0 port 1.0 pull-up resistor enable bit 0 disable pull-up resistor 1 enable pull-up resistor note: in order to use the open-drain output mode, the push-pull output bit in the p1conl should be set first.
control registers s3c9432/c9434/p9434 4 - 16 p 2 con ? port 2 control register e c h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7-.6 port 2 , p 2 . 3 configuration bits 0 0 push-pull output 0 1 push-pull output 1 0 open-drain output; pull-up resistor disable 1 1 open-drain output; pull-up resistor enable .5-.4 port 2 , p 2 . 2 configuration bits 0 0 push-pull output 0 1 push-pull output 1 0 open-drain output; pull-up resistor disable 1 1 open-drain output; pull-up resistor enable .3-.2 port 2 , p 2 . 1/so configuration bits 0 0 push-pull output 0 1 alternative function; so output 1 0 open-drain output; pull-up resistor disable 1 1 open-drain output; pull-up resistor enable .1- .0 port 2 , p 2 . 0 / sck configuration bits 0 0 push-pull output 0 1 alternative function; sck output 1 0 open-drain output; pull-up resistor disable 1 1 open-drain output; pull-up resistor enable note: p2.0/sck can be used only as the output mode, so it can not be used as the external clock input.
s3c9432/c9434/p9434 control registers 4 - 17 p wmcon ? pwm control register f4 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 ? ? 0 0 0 0 read/write r/w r/w ? ? r/w r/w r/w r/w .7-.6 pwm input clock selection bits 0 0 f osc /256 0 1 f osc /64 1 0 f osc /8 1 1 f osc /1 .5-.4 not used for the s3c9432/c9434/p9434 .3 pwm counter clear bit 0 no effect 1 clear the timer 0 counter (when write) pwm counter enable bit .2 0 stop counter 1 start (resume counting) pwm overflow interrupt enable bit (12-bit overflow) .1 0 disable interrupt 1 enable interrupt .0 pwm overflow interrupt pending bit 0 no interrupt pending 0 clear pending bit (write) 1 interrupt is pending
control registers s3c9432/c9434/p9434 4 - 18 siocon ? serial i/o module control register f0 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 sio shift clock selection bit 0 internal clock (p.s clock) 1 external clock (sck) .6 data direction control bit 0 msb first mode 1 lsb first mode .5 sio mode selection bit 0 receive-only mode 1 transmit/receive mode .4 shift clock edge selection bit 0 tx at falling edges, rx at rising edges 1 tx at rising edges, rx at falling edges .3 sio counter clear and shift start bit 0 no action 1 clear 3-bit counter and start shifting . 2 sio shift operation enable bit 0 disable shifter and clock counter 1 enable shifter and clock counter . 1 sio interrupt enable bit 0 disable sio interrupt 0 enable sio interrupt . 0 sio interrupt pending bit 0 no interrupt pending 0 clear pending condition (when write) 1 interrupt is pending
s3c9432/c9434/p9434 control registers 4 - 19 sym ? system mode register dfh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? 0 0 0 read/write ? ? ? ? ? r/w r/w r/w .7? .3 not used for s3c9432/c9434/p9434 .2 global interrupt enable bit (note) 0 disable all interrupt (di instruction) 1 enable all interrupt (ei instruction) .1- .0 page selection bits 0 0 page 0 0 1 page 1 (n ot used for s3c9432/c9434/p9434) 1 0 page 2 (n ot used for s3c9432/c9434/p9434) 1 1 page 3 (n ot used for s3c9432/c9434/p9434) note: after a reset, you enable global interrupt processing by executing an ei instruction (not by writing a 1 to sym.2).
control registers s3c9432/c9434/p9434 4 - 20 t0con ? timer 0 control register d3 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 ? ? 0 0 0 0 read/write r/w r/w ? ? r/w r/w r/w r/w .7-.6 timer 0 input clock selection bits 0 0 f osc /4096 0 1 f osc /256 1 0 f osc /8 1 1 t0ck .5-.4 note used for the s3c9432/c9434/p9434 .3 timer 0 counter clear bit 0 no effect 1 clears the timer 0 counter (when write) .2 note used for the s3c9432/c9434/p9434 .1 timer 0 interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer 0 interrupt pending bit (match interrupt) 0 no interrupt pending (when read) 0 clear pending bit (when write) 1 interrupt is pending (when read)
s3c9432/c9434/p9434 interrupt structure 5 - 1 5 interrupt structure overview the sam87ri interrupt structure has two basic components: a vector, and sources. the number of interrupt sources can be serviced through a n interrupt vector which is assigned in rom address 0000h. sources vector s1 s2 s3 sn 0000h 0001h notes: 1. the sam87ri interrupt has only one vector address (0000h-0001h). 2. the number of sn value is expandable. figure 5 - 1. s3c9 -series interrupt type interrupt processing control points interrupt processing can be controlled in two ways: either globally, or by specific interrupt level and source. the system-level control points in the interrupt structure are therefore: ? global interrupt enable and disable (by ei and di instructions) ? interrupt source en able and disable settings in the corresponding peripheral control register(s) enable/disable interrupt instructions (ei, di) the system mode register, sym (dfh), is used to enable and disable interrupt processing. sym.2 is the enable and disable bit for global interrupt processing respectively, by modifying sym.2. an enable interrupt (ei) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. although you can manipulate sym.2 directly to enable and disable interrupts during normal operation, we recommend that you use the ei and di instructions for this purpose.
interrupt structure s3c9432/c9434/p9434 5 - 2 interrupt pending function types when the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (iret) occurs. interrupt priority because there is not a interrupt priority register in sam87ri, the order of service is determined by a sequence of source which is executed in interrupt service routine. s r q interrupt pending register global interrupt control (ei, di instruction) vector interrupt cycle interrpt priority is determind by software polling method "ei" instruction execution reset source interrupts source interrupt enable figure 5 - 2. interrupt function diagram
s3c9432/c9434/p9434 interrupt structure 5 - 3 interrupt source service sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request pending bit to "1". 2. the cp u generates an interrupt acknowledge signal. 3. the service routine starts and the source's pending flag is cleared to "0" by software. 4. interrupt priority must be determined by software polling method. interrupt service routines before an interrupt request can be serviced, the following conditions must be met: ? interrupt processing must be enabled (ei, sym.2 = "1") ? interrupt must be enabled at the interrupt's source (peripheral control register) if all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the global interrupt enable bit in the sym register (di, sym.2 = "0") to disable all subsequent interrupts. 2. save the program counter and status flags to stack. 3. branch to the interrupt vector to fetch the service routine's address. 4. pass control to the interrupt service routine. when the interrupt service routine is completed, an interrupt return instruction (iret) occurs. the iret restores the pc and status flags and sets sym.2 to "1" (ei), allowing the cpu to process the next interrupt request. generating interrupt vector addresses the interrupt vector area in the rom contains the address of the interrupt service routine. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to stack. 2. push the program counter's high-byte value to stack. 3. push the flags register values to stack. 4. fetch the service routine's high-byte address from the vector address 0000h. 5. fetch the service routine's low-byte address from the vector address 0001h. 6. branch to the service routine specified by the 16-bit vector address.
interrupt structure s3c9432/c9434/p9434 5 - 4 s3c9432/c9434 interrupt structure the s3c9432/c9434 microcontroller has five peripheral interrupt sources: ? pwm overflow ? timer 0 match ? sio interrupt ? p0.2 external interrupt ? p0.3 external interrupt 0000h 0001h sym.2 (ei, di) p0pnd.1 t0con.0 pwmcon.0 siocon.0 p0pnd.0 timer 0 match pwm overflow sio interrupt p0.2 external interrupt p0.3 external interrupt t0con.1 pwmcon.1 siocon.1 p0con.5-.4 p0con.7-.6 sources vector pending bits enable/disable figure 5 - 3. s3c9432/c9434 interrupt structure
s3c9432/c9434/p9434 clock circuit 7 ? 1 7 clock circuit overview an rc oscillation source provides a typical 4 mhz cl ock for s3c9432/c9434 . an internal capacitor supports the rc oscillator circuit. an external crystal or ceramic oscilla tion source provides a maximum 16 mhz clock. the x in and x out pins connect the oscillation source to the on-chip clock circuit. simplified rc oscillator and crystal/ceramic oscillator circuits are shown in figures 7 - 1 and 7 - 2. x in x out s3c9432 /c9434 r figure 7 - 1. main oscillator circuit (rc oscillator with internal capacitor) x in x out s3c9432 /c9434 c1 c2 figure 7 - 2. main oscillator circuit (crystal/ceramic oscillator) main oscillator logic to increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator circuit. for this reason, very high resolution waveforms (square signal edges) must be generated in order for the cpu to efficiently process logic operations. clock status during power-down modes the two power-down modes, stop mode and idle mode, affect clock oscillation as follows: ? in stop mode, the main oscillator "freezes" , halting the cpu and peripherals. the contents of the register file and current system register values are retained. stop mode is released, and the oscillator started, by a reset operation or by an external interrupt with rc-delay noise filter (for s3c9432/c9434 , int0 - int1). ? in idle mode, the internal clock signal is gated off to the cpu, but not to interrupt control and the timer. the current cpu status is preserved, including stack pointer, program counter, and flags. data in the register file is retained. idle mode is released by a reset or by an interrupt (external or internally-generated).
clock circuit s3c9432/c9434/p9434 7 - 2 system clock control register (clkcon) the system clock control register, clkcon, is located in location d4h. it is read/write addressable and has the following functions: ? oscillator irq wake-up function enable/disable (clkcon.7) ? oscillator frequency divide-by value: non-divided, 2, 8, or 16 (clkcon.4 and clkcon.3) the clkcon register controls whether or not an external interrupt can be used to trigger a stop mode release (this is called the "irq wake-up" function). the irq wake-up enable bit is clkcon.7. after a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the f osc /16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can then increase the cpu clock speed to f osc , f osc /2 or f osc /8. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb system clock control register (clkcon) d4h, r/w not used for s3c9432/c9434/p9434 divide-by selection bits for cpu clock frequency: 00 = fosc/16 01 = fosc/8 10 = fosc/2 11 = fosc(non-divided) oscillator irq wake-up enable bit: 0 = enable irq for main system oscillator wake-up function in power down mode 1 = disable irq for main system oscillator wake-up function in power down mode not used for s3c9432/c9434/p9434 figure 7 - 3. system clock control register (clkcon)
s3c9432/c9434/p9434 clock circuit 7 - 3 main osc noise filter oscillator wake-up oscillator stop clkcon.7 int pin clkcon.4-.3 1/2 1/8 1/16 m u x stop instruction cup clock note: an external interrupt with an rc-delay nosie fillter can be used to release stop mode and "wake-up" the main oscillator . in the s3c9432/c9434, the int0-int1 external interrupts and sio interrupt are of this type. figure 7 - 4. system clock circuit diagram
s3c9432/c9434/p9434 reset reset and power-down 8 - 1 8 reset reset and power-down system reset overview the s3c9432/c9434 can be reset in four ways: ? by power-on reset ? by the external reset input pin pulled low ? by the digita l watchdog peripheral timing out ? by low voltage detection (lvd) during a power-on reset, the voltage at v dd is high level and the reset pin is forced to low level. the reset signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this brings the s3c9432/c9434 into a known operating status. to ensure correct start-up, the user should take care that reset signal is not released before the v dd level is sufficient to allow mcu operation at the chosen frequency. the reset pin must be held to low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal cpu clock oscillation to stabilize. the minimum required oscillation stabilization time for a reset is approximately 6.55 ms ( @ 2 1 6 / f osc , f osc = 10 mhz). when a reset occurs during normal operation (with both v dd and reset at high level), the signal at the reset pin is forced low and the reset operation starts. all system and peripheral control registers are then set to their default hardware reset values (see table 8 - 1). the mcu provides a watchdog timer function in order to ensure graceful recovery from software malfunction. if watchdog timer is not refreshed before an end-of-counter condition (overflow) is reached, the internal reset will be activated. the on-chip low voltage detector, features static reset when supply voltage is below a reference value (typ. 2.8 v). thanks to this feature, external reset circuit can be removed while keeping the application safety. as long as the supply voltage is below the reference value, there is a internal and static reset. the mcu can start only when the supply voltage rises over the reference value. note to program the duration of the oscillation stabilization interval, you must make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing " 1010b " to the upper nibble of btcon.
reset reset and power-down s3c9432/c9434/p9434 8 - 2 mcu initialization sequence the following sequence of events occurs during a reset operation: ? all interrupts are disabled. ? the watchdog function (basic timer) is enabled. ? port s 0-1 are set to input mode and all pull-up resistors are disabled. ? peripheral control and data registers are disabled an d reset to their initial values (see table 8-1). ? the program counter is loaded with the rom reset address, 0100h. ? when the programmed oscilla tion stabilization time interval has elapsed, the address stored in rom location 0100h (and 0101h) is fetched and executed. v dd watchdog 200 k w reset internal reset lvd figure 8-1. reset block diagram reset input oscillation stabilization wait time (6.55 ms/at 10 mhz) reset operation normal mode or power-down mode idle mode operation mode figure 8-2. timing for oscillation stabilization after reset reset
s3c9432/c9434/p9434 reset reset and power-down 8 - 3 power-down modes stop mode stop mode is invoked by the instruction stop (opcode 7fh). in stop mode, the operation of the cpu and all peripherals is halted. that is, the on-chip main oscillator stops and the supply current is reduced to less than 100 a. all system functions are halted when the clock "freezes" , but data stored in the internal register file is retained. stop mode can be released in one of two ways: by a reset signal or by an external interrupt. using reset reset to release stop mode stop mode is released when the reset signal is released and returns to high level. all system and peripheral control registers are then reset to their default values and the contents of all data registers are retained. a reset operation automatically selects a slow clock ( f osc / 16) because clkcon.3 and clkcon.4 are cleared to " 00b " . after the oscillation stabilization interval has elapsed, the cpu executes the system initialization routine by fetching the 16-bit address stored in rom locations 0100h and 0101h. using an external interrupt to release stop mode only external interrupts with an rc-delay noise filter circuit can be used to release stop mode (clock-related external interrupts cannot be used). external interrupts int0 - int1 in the s3c9432/c9434 interrupt structure meet this criteria. note that when stop mode is released by an external interrupt, the current values in system and peripheral control registers are not changed. when you use an interrupt to release stop mode, the clkcon.3 and clkcon.4 register values remain unchanged, and the currently selected clock value is used. if you use an external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must make the appropriate control and clock settings before entering stop mode. the external interrupt is serviced when the stop mode release occurs. following the iret from the service routine, the instruction immediately following the one that initiated stop mode is executed. idle mode idle mode is invoked by the instruction idle (opcode 6fh). in idle mode, cpu operations are halted while select peripherals remain active. during idle mode, the internal clock signal is gated off to the cpu, but not to interrupt logic and timer/counters. port pins retain the mode (input or output) they had at the time idle mode was entered. there are two ways to release idle mode: 1. execute a reset. all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects a slow clock ( f osc / 16) because clkcon.3 and clkcon.4 are cleared to " 00b " . if interrupts are masked, a reset is the only way to release idle mode. 2. activate any enabled interrupt, causing idle mode to be released. when you use an interrupt to release idle mode, the clkcon.3 and clkcon.4 register values remain unchanged, and the currently selected clock value is used. the interrupt is then serviced. following the iret from the service routine, the instruction immediately following the one that initiated idle mode is executed. note s 1. only external interrupts that are not clock-related can be used to release s top mode. to release idle mode, however, any type of interrupt (that is, internal or external) can be used. 2. before enter the stop or idle mode, the adc must be disabled. otherwise, the stop or idle current will be increased significantly.
reset reset and power-down s3c9432/c9434/p9434 8 - 4 hardware reset values table 8 - 1 list s the values for cpu and system registers, peripheral control registers, and peripheral data registers following a reset operation in normal operating mode. ? a "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. ? an "x" means that the bit value is undefined following a reset. ? a dash (" ? ") means that the bit is either not used or not mapped. table 8 - 1. register values a fter a reset register name mnemonic address bit values after reset reset 7 6 5 4 3 2 1 0 timer 0 counter register t0cnt d0h 0 0 0 0 0 0 0 0 timer 0 data register t0data d1h 1 1 1 1 1 1 1 1 timer 0 control register t0con d2h 0 0 0 0 0 0 0 0 location d3h is not mapped. clock control register clkcon d4h 0 0 0 0 0 0 0 0 system flags register flags d5h x x x x ? ? ? ? locations d6h-d8h are not mapped. stack pointer register sp d9h x x x x x x x x location dah is not mapped. mds special register mdsreg dbh 0 0 0 0 0 0 0 0 basic timer control register btcon dch 0 0 0 0 0 0 0 0 basic timer counter btcnt ddh 0 0 0 0 0 0 0 0 test mode control register ftstcon deh ? ? 0 0 0 0 0 0 system mode register sym dfh ? ? ? ? ? 0 0 0
s3c9432/c9434/p9434 reset reset and power-down 8 - 5 table 8 - 1. register values a fter a reset (continued) bank 0 register name mnemonic address bit values after a reset 7 6 5 4 3 2 1 0 port 0 data register p0 e0h ? ? ? ? 0 0 0 0 port 1 data register p1 e1h ? ? ? 0 0 0 0 0 port 2 data register p2 e2h ? ? ? ? 0 0 0 0 locations e3h-e5h are not mapped. port 0 control register p0con e6h 0 0 0 0 0 0 0 0 port 0 open-drain & pull-up control register p0 dpur e7h 0 0 0 0 0 0 0 0 port 0 interrupt pending register p0pnd e8h ? ? ? ? ? ? 0 0 port 1 control register (high byte) p1conh e9h ? ? ? ? ? 0 0 0 port 1 control register (low byte) p1conl eah 0 0 0 0 0 0 0 0 port 1 open-drain & pull-up control register p1dpur ebh 0 0 0 0 0 0 0 0 port 2 interrupt pending register p2con ech 0 0 0 0 0 0 0 0 locations edh-eeh are not mapped. sio data register siodata e f h 0 0 0 0 0 0 0 0 sio control register siocon f 0 h 0 0 0 0 0 0 0 0 sio prescaler siops f 1 h 0 0 0 0 0 0 0 0 pwm data register pwmdata f2h ? ? 0 0 0 0 0 0 pwm extension data register pwmex f3h 0 0 0 0 0 0 ? ? pwm control register pwmcon f4h 0 0 ? ? 0 0 0 0 location f5h is not mapped. prescaler for buzzer output buzps f6h 0 0 0 0 0 0 0 0 a/d control register adcon f7h ? 0 0 0 0 ? ? 0 a/d converter data register (high byte) addatah f8h x x x x x x x x a/d converter data register (low byte) addatal f9h 0 0 0 0 0 0 x x locations fa h -ff h are not mapped. note : "?" means not mapped, ?x? means undefined .
reset reset and power-down s3c9432/c9434/p9434 8 - 6 + + programming tip ? sample s3c9434 initialization routin ;--------------<< interrupt vector address >> org 0000h vector 00h,int_4304 ; s3c9434 has only one interrupt vector ;--------------<< initialize system and peripherals >> org 0100h reset: di ; disable interrupt ld btcon,#10100011b ; watch-dog disable ld clkcon,#00011000b ; select non-divided cpu clock ld sp,#60h ; stack pointer must be set ld p0con,#01011010b ; p0.3/0.2 input // p0.1/0.0 output ld p0dpur,#00001111b ; p0.0-0.3 pull-up enable ld p1conh,#00000100b ; p1.4 push-pull output ld p1conl,#00000000b ; p1.0-p1.3 schmitt trigger input ld p1dpur,#00001111b ; p1.0-p1.3 pull-up resistor enable ld p2con,#00000000b ; p2.0-p2.3 push-pull output ;--------------<< timer 0 settings >> ld t0data,#50h ; cpu = 11.0592mhz, interrupt interval = 2 msec ld t0con,#01001010b ; fosc/256, timer0 interrupt enable ;--------------<< clear all data registers from 00h to 5fh >> ld r0,#0 ; ram clear ram_clr: clr @r0 ; inc r0 ; cp r0,#5fh ; jp ule,ram_clr ;--------------<< initialize other registers >> ei ; enable interrupt
s3c9432/c9434/p9434 reset reset and power-down 8 - 7 + + programming tip ? sample s3c9434 initialization routine (continued) ;--------------<< main loop >> main: nop ; start main loop ld btcon,#02h ; enable watchdog function ; basic counter (btcnt) clear call key_scan ; sub-block module call led_display ; sub-block module call job ; sub-block module j r t,main ; ;--------------<< subroutines >> key_scan: nop ; sub-block module ret led_display: nop ; sub-block module ret job: nop ; sub-block module ret
reset reset and power-down s3c9432/c9434/p9434 8 - 8 + + programming tip ? sample s3c9434 initialization routine (continued) ;--------------<< interrupt service routines >> ; interrupt enable bit and pending bit check int_4304: tm t0con,#00000010b ; timer0 interrupt enable check jr z,next_chk1 ; tm t0con,#00000001b ; if timer0 interrupt was occurred, jp nz,int_timer0 ; t0con.0 bit would be set. next_chk1: tm siocon,#00000010b ; sio interrupt enable check jr z,next_chk2 ; tm siocon,#00000001b ; jp nz,sio_int ; next_chk2: tm pwmcon,#00000010b ; pwm overflow interrupt enable check jr z,next_chk3 ; tm pwmcon,#00000001b ; jp nz,pwmovf_int ; next_chk3: tm p0pnd,#00000001b ; jp nz,int0_int ; tm p0pnd,#00000010b ; jp nz,int1_int ; iret ; interrupt return ;--------------< timer0 interrupt service routine > int_timer0: ; and t0con,#11110110b ; pendi ng bit clear iret ; interrupt return ;--------------< sio interrupt service routine > sio_int: and siocon,#11111110b ; pending bit clear iret ; interrupt return ;--------------< pwm overflow interrupt service routine > pwmovf_int: and pwmcon,#11111110b ; pending bit clear iret ; interrupt return
s3c9432/c9434/p9434 reset reset and power-down 8 - 9 + + programming tip ? sample s3c9434 initialization routine (continued) ;--------------< external interrupt0 service routine > int0_int: ld p0pnd,#00000010b ; int0 pending bit clear iret ; interrupt return ;--------------< external interrupt1 service routine > int0_int: ld p0pnd,#00000001b ; int1 pending bit clear iret ; interrupt return end ;
s3c9432/c9434/p9434 i/o ports 9 - 1 9 i/o ports overview the s3c9432/c9434 has two i/o ports and one output port: with 13 pins total. you access these ports directly by writing or reading port data register addresses. all ports can be configured as led drive. (high current output: typical 10 ma) table 9 - 1. s3c9432/c9434 port configuration overview port function description programmability 0 bit-programmable i/o port for schmitt trigger input or push-pull, open- drain output. pull-up resistors are assignable by software. port0 pins can also be used as alternative function. bit 1 bit-programmable i/o port for schmitt trigger input or push-pull, open- drain output. pull-up resistors are assignable by software. port1 pins can also be used as a/d converter input or alternative function. bit 2 p ush-pul l or open drain only output port. pull-up resistors are assignable by software. port2 can also be used as alternative function. bit
i/o ports s3c9432/c9434/p9434 9 - 2 port data registers table 9 - 2 gives you an overview of the port data register names, locations, and addressing characteristics. data registers for ports 0 -2 have the structure shown in figure 9 - 1. table 9 - 2. port data register summary register name mnemonic hex r/w port 0 data register p0 e0h r/w port 1 data register p1 e1h r/w port 2 data register p2 e2h r/w note: a reset operation clears the p0-p2 data register to "00h". .7 .6 .5 .4 .3 .2 .1 .0 lsb msb i/o port n data register (n = 0-2) pn.0 pn.1 pn.2 pn.4 pn.3 pn.5 pn.6 pn.7 figure 9 - 1. port data register format
s3c9432/c9434/p9434 i/o ports 9 - 3 port 0 port 0 is a bit-programmable, general-purpose, i/o ports. you can select normal input or push-pull, o pen drain output mode. in addition, you can configure a pull-up resistor to individual pins using control register settings. it is designed for high-current functions such as led direct drive. you access port 0 directly by writing or reading the c orresponding port data register, p0 (e0h). a reset c lears the port control register, p0con , to " 00h " configuring port 0 pins as normal input s. two addition resisters are used to control port 0: p0dpur (e7h) and p0pnd (e8h). by setting bits in the port 0 open-drain enable register p0dpur, you can configure specific pin as a open-drain output. v dd v dd open-drain buz, pwm noise filter output disable (input mode) circuit type a pull-up register (47 k w typical) i/o note: i/o pins have protection diodes through v dd and v ss . mode d0 d1 input data output input m u x pull-up enable p0 data external interrupt input input data p0con mux d0 d1 figure 9-2. port 0 circuit diagram
i/o ports s3c9432/c9434/p9434 9 - 4 .7 .6 .5 .4 .3 .2 .1 .0 lsb msb port 0 control registers e6h, r/w [.7-.6] port 0, p0.3/int1 configuration bits 00 = schmitt trigger input; int1 interrupt disable 01 = schmitt trigger input; interrupt on falling edge 10 = push-pull output 11 = schmitt trigger input; interrupt on rising edge [.5-.4] port 0, p0.2/int0 configuration bits 00 = schmitt trigger input (t0ck input); int0 interrupt disable 01 = schmitt trigger input (t0ck input); interrupt on falling edge 10 = push-pull output 11 = schmitt trigger input (t0ck input); interrupt on rising edge [.3-.2] port0, p0.1/pwm configuration bits 00 = schmitt trigger input 01 = schmitt trigger input 10 = push-pull output 11 = alternative function (pwm output) [.1-.0] port0, p0.0/buz configuration bits 00 = schmitt trigger input 01 = schmitt trigger input 10 = push-pull output 11 = alternative function (buz output) figure 9 -3 . port 0 c ontrol register (p0con )
s3c9432/c9434/p9434 i/o ports 9 - 5 msb .7 .6 .5 .4 .3 .2 .1 .0 lsb port 0 n-channel open-drain enable register e7h, r/w [.7] port 0.3/int1 n-channel open-drain enable bit 0 = configure p0.3 as a push-pull output 1 = configure p0.3 as a n-channel open-drain output [.6] port 0.2/t0ck/int0 n-channel open-drain enable bit 0 = configure p0.2 as a push-pull output 1 = configure p0.2 as a n-channel open-drain output [.5] port 0.1/pwm n-channel open-drain enable bit 0 = configure p0.1 as a push-pull output 1 = configure p0.1 as a n-channel open-drain output [.4] port 0.0/buz n-channel open-drain enable bit 0 = configure p0.0 as a push-pull output 1 = configure p0.0 as a n-channel open-drain output [.3] port 0.3/int1 pull-up resistor enable bit 0 = disable pull-up resistor 1 = enable pull-up resistor [.2] port 0.2/t0ck/int0 pull-up resistor enable bit 0 = disable pull-up resistor 1 = enable pull-up resistor [.1] port 0.1/pwm pull-up resistor enable bit 0 = disable pull-up resistor 1 = enable pull-up resistor [.0] port 0.0/buz pull-up resistor enable bit 0 = disable pull-up resistor 1 = enable pull-up resistor figure 9 -4 . port 0 n-channel open-drain enable register (p0dpur )

s3c9432/c9434/p9434 i/o ports 9 - 7 .7 .6 .5 .4 .3 .2 .1 .0 lsb msb port 0 interrupt pending register e8h, r/w [.7-.2] not used for s3c9432/c9434/p9434 [.1] port 0.3/int1, interrupt pending bit 0 = no interrupt pending (when read) 0 = pending bit clear (when write) 1 = interrupt is pending (when read) [.1] port 0.2/int0, interrupt pending bit 0 = no interrupt pending (when read) 0 = pending bit clear (when write) 1 = interrupt is pending (when read) figure 9 -5 . port 0 interrupt pending registers (p0pnd )

s3c9432/c9434/p9434 i/o ports 9 - 9 port 1 port 1, is a 5-bit i/o port with individually configurable pins. it can be used for general i/o port (schmitt trigger input mode , push-pull output mode or n-channel open-drain output mode) . you can also use port1 as special input (adc, si or sck) or output (so, sck, clo). in addition, you can configure a pull-up resistor to individual pin using control register settings. it is designed for high-current functions such as led direct drive. in normal operating mode, a reset clears p 1conh and p1conl to "00h", configuring p1 .0 - p 1 . 4 as normal schmitt trigger input s. you address port 1 bits directly by writing or reading the port 1 data register, p1 (e 1h). v dd v dd open-drain so, sck, clo output disable (input mode) circuit type a pull-up register (47 k w typical) i/o note: i/o pins have protection diodes through v dd and v ss . mode d0 d1 input data output input m u x pull-up enable p1 data to adc input data p1con mux d0 d1 figure 9-6. port 1 circuit diagram
i/o ports s3c9432/c9434/p9434 9 - 10 .7 .6 .5 .4 .3 .2 .1 .0 lsb msb port 1 control register (high-byte) e9h, r/w [.7-.3] not used for s3c9432/c9434/p9434 [.2-.0] port 1, p1.4/adc4/clo configuration bits 00x = schmitt trigger input 010 = schmitt trigger input; pull-up enable 011 = a/d converter input (adc4); schmitt trigger input off 100 = push-pull output 101 = open-drain output 110 = open-drain output; pull-up enable 111 = alternative function; clo output figure 9 -7 . port 1 high-byte control register (p1con h )
s3c9432/c9434/p9434 i/o ports 9 - 11 .7 .6 .5 .4 .3 .2 .1 .0 lsb msb port 1 control register (low-byte) eah, r/w [.7-.6] port 1, p1.3/adc3/sck configuration bits 00 = schmitt trigger input; sck input 01 = alternative function; sck output 10 = push-pull output 11 = a/d converter input (adc3); schmitt trigger input off [.5-.4] port 1, p1.2/adc2/so configuration bits 00 = schmitt trigger input 01 = alternative function; so output 10 = push-pull output 11 = a/d converter input (adc2); schmitt trigger input off [.3-.2] port 1, p1.1/adc1/si configuration bits 00 = schmitt trigger input; si input 01 = schmitt trigger input; si input 10 = push-pull output 11 = a/d converter input (adc1); schmitt trigger input off [.1-.0] port 1, p1.0/adc0 configuration bits 00 = schmitt trigger input 01 = schmitt trigger input 10 = push-pull output 11 = a/d converter input (adc0); schmitt trigger input off figure 9-8. port 1 low-byte control register (p1conl)
i/o ports s3c9432/c9434/p9434 9 - 12 msb .7 .6 .5 .4 .3 .2 .1 .0 lsb port 1 open-drain pull-up control register ebh, r/w [.7] port 1.3, n-channel open-drain enable bit 0 = configure p1.3 as a push-pull output 1 = configure p1.3 as a n-channel open-drain output [.6] port 1.2, n-channel open-drain enable bit 0 = configure p1.2 as a push-pull output 1 = configure p1.2 as a n-channel open-drain output [.5] port 1.1, n-channel open-drain enable bit 0 = configure p1.1 as a push-pull output 1 = configure p1.1 as a n-channel open-drain output [.4] port 1.0, n-channel open-drain enable bit 0 = configure p1.0 as a push-pull output 1 = configure p1.0 as a n-channel open-drain output [.3] port 1.3, pull-up resistor enable bit 0 = disable pull-up resistor 1 = enable pull-up resistor [.2] port 1.2, pull-up resistor enable bit 0 = disable pull-up resistor 1 = enable pull-up resistor [.1] port 1.1, pull-up resistor enable bit 0 = disable pull-up resistor 1 = enable pull-up resistor [.0] port 1.0, pull-up resistor enable bit 0 = disable pull-up resistor 1 = enable pull-up resistor figure 9-9. port 1 open-drain & pull-up control register (p1dpur)
s3c9432/c9434/p9434 i/o ports 9 - 13 port 2 port 2 is a 4 -bit output port with individually configurable pins. it can be used for general output port (push-pull output mode or n-channel open-drain output mode). y ou can also use port 2 pins as serial clock output or serial data output pin . in addition, you can configure a pull-up resistor to individual pins using control register settings. it is designed for high-current functions such as led direct drive. in normal opera ting mode, a reset clears p2con to " 00h " , configuring p2.0 - p2.3 as push-pull output . you address port 2 bits directly by writing or reading the port 2 data register, p2 (e2h). the port 2 control register, p2con is located at addresses e c h. v dd v dd open-drain so, sck output only (low) pull-up register (47 k w typical) i/o note: i/o pins have protection diodes through v dd and v ss . m u x pull-up enable p2 data p2con figure 9-10. port 2 circuit diagram
i/o ports s3c9432/c9434/p9434 9 - 14 .7 .6 .5 .4 .3 .2 .1 .0 lsb msb port 2 control register ech, r/w [.7-.6] port 2, p2.3 configuration bits 00 = push-pull output 01 = push-pull output 10 = open-drain output; pull-up resistor disable 11 = open-drain output; pull-up resistor enable [.5-.4] port 2, p2.2 configuration bits 00 = push-pull output 01 = push-pull output 10 = open-drain output; pull-up resistor disable 11 = open-drain output; pull-up resistor enable [.3-.2] port 2, p2.1/so configuration bits 00 = push-pull output 01 = alternative function; so output 10 = open-drain output; pull-up resistor disable 11 = open-drain output; pull-up resistor enable [.1-.0] port 2, p2.0/sck configuration bits 00 = push-pull output 01 = alternative function; sck output 10 = open-drain output; pull-up resistor disable 11 = open-drain output; pull-up resistor enable figure 9 -11 . port 2 control registers (p2con)
s3c9432/c9434/p9434 basic timer and timer 0 10 - 1 10 basic timer and timer 0 module overview the s3c9432/c9434 has two default timers: an 8-bit basic timer , one 8-bit general-purpose timer/counter, called ti mer 0 . basic timer (bt) you can use the basic timer (bt) in two different ways: ? as a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. ? to signal the end of the required oscillation stabilization interval after a reset or a stop mode release. the functional components of the basic timer block are: ? clock frequency divider (f osc divided by 409 6, 1024, or 128) with multiplexe r ? 8-bit basic timer counter, btcnt (ddh, read-only) ? basic timer control register, btcon (dch, read/write) timer 0 timer 0 has the following functional components: ? clock frequency divider (f osc divided by 4096, 256, 8, or t0ck ) with multiplexer ? 8-bit counter (t0cnt), 8-bit comparato r, and 8 -bit data register (t0data) ? timer 0 control register ( t0con )
basic timer and timer 0 s3c9432/c9434/p9434 10 - 2 basic timer (bt) basic timer control register (btcon) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. a reset clears btcon to " 00h " . this enables the watchdog function and selects a basic timer clock frequency of f osc /4096. to disable the watchdog function, you must write the signature code " 1010b " to the basic timer register control bits btcon.7 - btcon.4. the 8-bit basic timer counter, btcnt, can be cleared during normal operation by writing a "1" to btcon.1. to clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you write a "1" to btcon.0. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb basic timer control register (btcon) dch, r/w watchdog timer enable bits: 1010b = disable watchdog function other value = enable watchdog function basic timer counter clear bit: 0 = no effect 1 = clear basic timer counter basic timer input clock selection bits: 00 = fosc/4096 01 = fosc/1024 10 = fosc/128 11 = invalid selection divider clear bit for basic timer and timer 0: 0 = no effect 1 = clear both dividers note: when you write a 1 to btcon.0 (or btcon.1), the basic timer divider (or basic timer counter) is cleared. the bit is then cleared automatically to 0. figure 10-1. basic timer control register (btcon)
s3c9432/c9434/p9434 basic timer and timer 0 10 - 3 basic timer function description watchdog timer function you can program the basic timer overflow signal (btovf) to generate a reset by setting btcon.7 - btcon.4 to any value other than " 1010b " (the " 1010b " value disables the watchdog function). a reset clears btcon to " 00h " , automatically enabling the watchdog timer function. a reset also selects the cpu clock (as determined by the current ccon register setting) divided by 4096 as the bt clock. a reset whenever a basic timer counter overflow occurs. during normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. to do this, the btcnt value must be cleared (by writing a "1" to btcon.1) at regular intervals. if a system malfunction occurs due to circuit noise or some other error condition, the bt counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. in other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, btcnt) is always broken by a btcnt clear instruction. if a malfunction does occur, a reset is triggered automatically. oscillation stabilization interval timer function you can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. in stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. the btcnt value then starts increasing at the rate of f osc /4096 (for reset), or at the rate of the preset clock source (for an external interrupt). when btcnt.4 i s set , a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the cpu so that it can resume normal operation. in summary, the following events occur when stop mode is released: 1. during stop mode, a power-on reset or an external interrupt occurs to trigger the stop mode release and oscillation starts. 2. if a power-on reset occurred, the basic timer counter will increase at the rate of f osc /4096. if an external interrupt is used to release stop mode, the btcnt value increases at the rate of the preset clock source. 3. clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter i s set . 4. when a btcnt.4 i s set , normal cpu operation resumes. figure 10 - 2 and 10 - 3 shows the oscillation stabilization time on reset and stop mode release
basic timer and timer 0 s3c9432/c9434/p9434 10 - 4 oscillation stabilization time normal operating mode 0.8 v dd t wait = 4096x16x1/f osc basic timer increment and cpu operations are idle mode 10000b 00000b reset release voltage note: duration of the oscillator stabilization wait time, t wait , when it is released by a power-on-reset is 4096 x 16/f osc . t rst rc (r is external resistor and c is on chip capacitor) v dd resetb internal reset release oscillator (x out ) btcnt clock btcnt value 0.8 v dd oscillator stabilization time trst ~ rc ~ ~ ~ figure 10- 2. oscillation stabilization time on reset reset
s3c9432/c9434/p9434 basic timer and timer 0 10 - 5 note: duration of the oscillator stabilzation wait time, twait, it is released by an interrupt is determined by the setting in basic timer control register, btcon. v dd oscillation stabilization time resetb external interrupt oscillator (x out ) btcnt clock btcnt value t wait basic timer increment 10000b stop release signal 00000b normal operating mode normal operating mode stop mode stop mode release signal stop instruction execution btcon.3 btcon.2 0 0 1 1 0 1 0 1 t wait 4096 x 16/fosc 1024 x 16/fosc 128 x 16/fosc invalid setting t wait (when f osc is 10 mhz) 6.55 ms 1.64 ms 0.2 ms figure 10 - 3. oscillation stabilization time on stop mode release
basic timer and timer 0 s3c9432/c9434/p9434 10 - 6 + + programming tip ? configuring the basic timer this example shows how to configure the basic timer to sample specification . org 0000h vector 00h,int_4304 ; s3c9434 has only one interrupt vector ;--------------<< initialize system and peripherals >> org 0100h reset: di ; disable interrupt ld clkcon,#00011000b ; select non-divided cpu clock ld sp,#60h ; stack pointer must be set ld btcon,#02h ; enable watchdog function ; basic timer clock: fosc/4096 ; basic counter (btcnt) cl ear ei ; enable interrupt ;--------------<< main loop >> main: ld btcon,#02h ; enable watchdog function ; basic counter (btcnt) clear jr t,main ; ;--------------<< interrupt service routines >> int_4304: ; interrupt enable bit and pending bit check ; ; pending bit clear iret ; end ;
s3c9432/c9434/p9434 basic timer and timer 0 10 - 7 timer 0 timer 0 control register s (t0con) the timer 0 control register, t0con, is used to select the timer 0 operating mode (interval timer ) and input clock frequency, to clear the timer 0 counter, and to enable the t0 match interrupt. it also contains a pending bit for t0 match interrupts. a reset clears t0con to " 00h " . this sets timer 0 to normal interval timer mode, selects an input clock frequency of f osc /4096, and disables the t0 match interrupts. the t0 counter can be cleared at any time during normal operation by writing a "1" to t0con.3. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb timer 0 control register d3h, r/w timer 0 interrupt pending bit: 0 = no t0 interrupt pending (when read) 0 = clear t0 pending bit (when write) 1 = t0 interrupt is pending (when read) timer 0 input clock selection bits: 00 = fosc/4096 01 = fosc/256 10 = fosc/8 11 = t0ck not used for the s3c9432/c9434/p9434 timer 0 counter clear bit: 0 = no effect 1 = clear the timer 0 counter (when write) not used for the s3c9432/c9434/p9434 timer 0 interrupt enable bit: 0 = disable t0 interrupt 1 = enable t0 interrupt figure 10 -4 . timer 0 control register s (t0con)
basic timer and timer 0 s3c9432/c9434/p9434 10 - 8 timer 0 function description interval timer mode in interval timer mode, a match signal is generated when the counter value is identical to the value written to the t imer 0 reference data register, t0data. the match signal generates a t imer 0 m atch interrupt (t0int, vector 00 h) and then clears the counter. if, for example, you write the value " 10h " to t0data, the counter will increment until it reaches " 10h " . at this point, the t imer 0 interrupt request is generated, the counter value is reset and counting resumes. counter (t0cnt) comparator clk data register (t0data) r (clear) match interrupt enable/disable irq0 (t0int) pnd t0con.3 figure 10 -5 . simplified timer 0 function diagram (interval timer mode)
s3c9432/c9434/p9434 basic timer and timer 0 10 - 9 interrupt request (t0con.0) counter clear (t0con.3) match compare value (t0data) match match up counter value (t0cnt) 00h count start t0con .3 <-1 match match match match clear clear t0data value change clear figure 10-6. timer 0 timing diagram
basic timer and timer 0 s3c9432/c9434/p9434 10 - 10 irq0 x in x in mux mux div r 1/4096 t0ck 1/8 1/256 t0cnt (d0h) (read-only) 8-bit comparator bit 0 bit 1 bit 3 clear data bus bits 7, 6 bit 0 8-bit up counter (btcnt, read-only) div r ovf bits 3, 2 1/4096 1/1024 1/128 bit 1 reset or stop reset data bus clear when btcnt.4 is set after releasing from reset or stop mode, cpu clock starts. match basic timer control register (write '1010xxxxb' to disable.) note: during a power-on reset operation, the cpu is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter is set). t0data (d1h) (read/write) data bus t0data buffer t0con.3 (when write) match signal basic timer control register timer 0 control register figure 10 -7 . basic timer and timer 0 block diagram
s3c9432/c9434/p9434 basic timer and timer 0 10 - 11 + + programming tip1 -- configuring timer 0 (interval mode) the following sample program sets timer 0 to interval timer mode. org 0000h vector 00h,int_4304 ; s3c9434 has only one interrupt vector org 0100h reset: di ; disable interrupt ld btcon,#10100011b ; watch-dog disabl e ld clkcon,#00011000b ; select non-divided cpu clock ld sp,#60h ; set stack pointer ld p0con,#01011010b ; p0.3/0.2 input // p0.1/0.0 output ld p0dpur,#00001111b ; p0.0 - 0.3 pull-up enable ld p1conh,#00000100b ; p1.4 push-pull output ld p1conl,#00000000b ; p1.0 - p1.3 schmitt trigger input ld p1dpur,#00001111b ; p1.0 - p1.3 pull-up resistor enable ld p2con,#00000000b ; p2.0 - p2.3 push-pull output ;--------------<< timer 0 settings >> ld t0data,#50h ; cpu = 11.0592mhz, interrupt inte rval = 2 msec ld t0con,#01001010b ; fosc/256, timer0 interrupt enable ei ; enable interrupt ;--------------<< main loop >> main: nop ; start main loop call led_display ; sub-block module call job ; sub-block module jr t,main ;
basic timer and timer 0 s3c9432/c9434/p9434 10 - 12 + + programming tip1 -- configuring timer 0 (interval mode) (continued) led_display: nop ; ; ; ; ret ; job: nop ; ; ; ; ret ; ;--------------<< interrupt service routines >> int_4304: tm t0con,#00000010b ; interrupt enable check jr z,next_chk1 ; tm t0con,#00000001b ; if timer0 interrupt was occurred, jp nz,int_timer0 ; t0con.0 bit would be set. next_chk1: ; interrupt enable bit and pending bit check ; ; iret ; int_timer0: ; timer0 interrupt service routine and t0con,#11110110b ; pending bit clear iret ; end ;
s3c9432/c9434/p9434 12-bit pwm 11- 1 1 1 12-bit pwm (pulse width modulation) overview this microcontroller has the 12-bit pwm circuit. the operation of all pwm circuit is controlled by a single control register, pwmcon. the pwm counter is a 12-bit incrementing counter. it is used by the 12-bit pwm circuits. to start the counter and enable the pwm circuits, you set pwmcon.2 to "1". if the counter is stopped, it retains its current count value; when re-started, it resumes counting from the retained count value. when there is a need to clear the counter you set pwmcon.3 to "1". you can select a clock for the pwm counter by set pwmcon.6-.7. clocks which you can select are f osc /256, f osc /64, f osc /8, f osc /1. function description pwm the 12-bit pwm circuits ha ve the following components: ? 6-bit comparator and extension cycle circuit ? 6 -bit reference data registers (pwmdata) ? 6 -bit extension data registers (pwmex) ? pwm output pins ( p0.1/ pwm) pwm counter the pwm counter is a 12-bit incrementing counter comprised of a lower 6-bit counter and an upper 6-bit counter. to determine the pwm module's base operating frequency, the lower byte counter is compared to the pwm data register value. in order to achieve higher resolutions, the six bits of the upper counter can be used to modulate the "stretch" cycle. to control the "stretching" of the pwm output duty cycle at specific intervals, the 6-bit extended counter value is compared with the 6-bit value (bits 7-2) that you write to the module's extension register.
12-bit pwm s3c9432/c9434/p4304 1 1- 2 pwm data and extension registers pwm (duty) data registers, located in f2h, determine the output value generated by each 12-bit pwm circuit. these registers, pwm is read/write addressable. ? 8-bit data register pwmdata, of which only bits 5-0 are used. ? 8-bit extension registers pwmex (f3h), of which only bits 7-2 are used to program the required pwm output, you load the appropriate initialization values into the 6-bit data registers (pwmdata) and the 6-bit extension registers (pwmex). to start the pwm counter, or to resume counting, you set pwmcon.2 to "1". a reset operation disables all pwm output. the current counter value is retained when the counter stops. when the counter starts, counting resumes at the retained value. pwm clock rate the timing characteristics of both 12-bit output channels are identical, and are based on the f osc clock frequency. the counter clock value is determined by the setting of pwmcon.6-.7. table 11-1. pwm control and data registers register name mnemonic address function pwm data registers pwmdata f2h 6-bit pwm basic cycle frame value pwmex f3h 6-bit extension ("stretch") value pwm control registers pwmcon f4h pwm counter stop/start (resume), and f osc clock settings pwm function description the pwm output signal toggles to low level whenever the lower 6-bit counter matches the reference value stored in the module's data register (pwmdata). if the value in the pwmdata register is not zero, an overflow of the lower counter causes the pwm output to toggle to high level. in this way, the reference value written to the data register determines the module's base duty cycle. the value in the 6-bit extension counter is compared with the extension settings in the 6-bit extension data register (pwmex). this 6-bit extension counter value, together with extension logic and the pwm module's extension register , is then used to "stretch" the duty cycle of the pwm output. the "stretch" value is one extra clock period at specific intervals, or cycles (see table 11-2). if, for example, the value in the extension register is '04h', the 32nd cycle will be one pulse longer than the other 63 cycles. if the base duty cycle is 50 %, the duty of the 32nd cycle will therefore be "stretched" to approximately 51% duty. for example, if you write 80h to the extension register, all odd-numbered pulses will be one cycle longer. if you write fch to the extension register, all pulses will be stretched by one cycle except the 64th pulse. pwm output goes to an output buffer and then to the corresponding pwm output pin. in this way, you can obtain high output resolution at high frequencies.
s3c9432/c9434/p9434 12-bit pwm 11- 3 table 11-2. pwm output "stretch" values for extension registers pwm0ex pwm0ex bit "stretched" cycle number 7 1, 3, 5, 7, 9, . . . , 55, 57, 59, 61, 63 6 2, 6, 10, 14, . . . , 50, 54, 58, 62 5 4, 12, 20, . . . , 44, 52, 60 4 8, 24, 40, 56 3 16, 48 2 32 1 not used 0 not used pwm clock: 4 mhz 250 ns 0h 1h 20h 3fh 8 m s 0h pwm data register values: 40h 80h 250 ns 250 ns 8 m s figure 11-1. 12-bit pwm basic waveform
12-bit pwm s3c9432/c9434/p4304 1 1- 4 pwm clock: 500 ns 1st 0h pwmdata register values: 02h 40h 32th 64th 1st 32th 64th 750 ns 0h 40h 2h 4 mhz pwmex register values: 04h 4 mhz figure 11-2. 12-bit extended pwm waveform
s3c9432/c9434/p9434 12-bit pwm 11- 5 pwm control register (pwmcon) the control register for the pwm module, pwmcon, is located at register address f 4 h . pwmcon is used the 12-bit pwm modules. bit settings in the pwmcon register control the following functions: ? pwm counter clock selection ? pwm data reload interval selection ? pwm counter clear ? pwm counter stop/start (or resume) operation ? pwm counter overflow (upper 6-bit counter overflow) interrupt control a reset clears all pwmcon bits to logic zero, disabling the entire pwm module. lsb msb pwm control registers (pwmcon) f4h, reset: 00h pwm counter interrupt enable bit: 0 = disable pwm ovf interrupt 1 = enable pwm ovf interrupt pwm 12-bit ovf interrupt pending bit: 0 = no interrupt pending 0 = clear pending condition (when write) 1 = interrupt is pending .7 .6 .5 .4 .3 .2 .1 .0 pwm input clock selection bits: 00 = fosc/256 01 = fosc/64 10 = fosc/8 11 = fosc/1 pwm counter clear bit: 0 = no effect 1 = clear the 12-bit up counter pwm counter enable bit: 0 = stop counter 1 = start (resume countering) not used for s3c9432/c9434/p9434 figure 1 1- 3. pwm/capture module control register (pwmcon)
12-bit pwm s3c9432/c9434/p4304 1 1- 6 6-bit basic register pwmdata 6-bit buffer 6 6 lower 6-bit counter mux pwmcon.6-7 6 upper 6-bit counter p0.1/pwm pwmcon.2 fosc/256 fosc/64 fosc/8 fosc/1 "1" when reg > counter "0" when reg < counter reload (overflow of the lower 6-bit counter) extension control logic (1,3,...,61,63) 32 bit 2 bit 7 6-bit extension registers (pwmex) 6-bit comparator pwmdata = counter ovfint pending pwmcon.0 pwmcon.1 = figure 1 1- 4. pwm/capture module functional block diagram
s3c9432/c9434/p9434 12-bit pwm 11- 7 + + programming tip ? programming the pwm module to sample specifications org 0000h vector 00h,int_4304 ; s3c9434 has only one interrupt vector ;--------------<< initialize system and peripherals >> org 0100h reset: di ; disable interrupt ld btcon,#10100011b ; watch-dog disable ld p0con,#00001100b ; configure p0.1 pwm output ld pwmcon,#00000110b ; fosc/256, counter/interrupt enabl e ld pwmdata,#10h ; set value between 00h - 3fh ld pwmex,#80h ; .1/.0 bit are not used ei ; enable interrupt ;--------------<< main loop >> main: ; ; ; ; ; jr t,main ; ;--------------<< interrupt service routines >> int_4304: ; interrupt enable bit and pending bit check tm pwmcon,#00000010b ; interrupt enable check jr z,next_chk1 ; tm pwmcon,#00000001b ; interrupt pending bit check jp nz,int_pwm ; pwmcon's pending bit set --> pwm interrupt next_chk1: iret ;
12-bit pwm s3c9432/c9434/p4304 1 1- 8 + + programming tip ? programming the pwm module to sample specifications (continued) int_pwm: ; pwm interrupt service routine and pwmcon,#11110110b ; pending bit clear iret ; end
s3c9432/c9434/p9434 a/d converter 12- 1 1 2 a/d converter overview the 10-bit a/d converter (adc) module uses successive approximation logic to convert analog levels entering at one of the five input channels to equivalent 10-bit digital values. the analog input level must lie between the av ref and av ss values. the a/d converter has the following components: ? analog comparator with successive approximation logic ? d / a converter logic ? adc control register (adcon) ? five multiplexed analog data input pins (adc0 - adc 4 ) ? 10-bit a/d conversion data output register (addatah/l ) : ? av ref and av ss pins to initiate an analog-to-digital conversion procedure, you write the channel selection data in the a/d converter control register adcon to select one of the five analog input pins (adcn, n = 0-4) and set the conversion start or enable bit, adcon.0. the read-write adcon register is located at address f7h. during a normal conversion, adc logic initially sets the successive approximation register to 200h (the approximate half-way point of an 10-bit register). this register is then updated automatically during each conversion step. the successive approximation block performs 10-bit conversions for one input channel at a time. you can dynamically select different channels by manipulating the channel selection bit value (adcon.7- 4) in the adcon register. to start the a/d conversion, you should set a the enable bit, adcon.0. when a conversion is completed, acon.3, the end-of-conversion (eoc) bit is automatically set to 1 and the result is dumped into the addata register where it can be read. the a/d converter then enters an idle state. remember to read the contents of addata before another conversion starts. otherwise, the previous result will be overwritten by the next conversion result. note because the adc does not use sample-and-hold circuitry, it is important that any fluctuations in the analog level at the adc0 - adc 4 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to circuit noise, will invalidate the result.
a/d converter s3c9432/c9434/p943 4 12- 2 using a/d pins for standard digital input the adc module's input pins are alternatively used as digital input in port 1. the adc0 -adc4 share pin names are p 1 .0 -p1.4. a/d converter control register (adcon) the a/d converter control register, adcon, is located at address f 7 h. adcon has four functions: ? bits 7- 4 select an analog input pin (adc0 - adc 4). ? bit 3 indicates the status of the a/d conversion. ? bits 2-1 select a conversion speed. ? bit 0 starts the a/d conversion. only one analog input channel can be selected at a time. you can dynamically select any one of the five analog input pins (adc0 -adc4 ) by manipulating the 4-bit value for adcon.7- adcon.4 . lsb msb a/d converter control register (adcon) f7h, r/w end-of-conversion (eoc) status bit: 0 = a/d conversion is in progress 1 = a/d conversion complete conversion start bit: 0 = no effect 1 = a/d conversion start .7 .6 .5 .4 .3 .2 .1 .0 a/d converter input pin selection bits: 0000 adc0 (p1.0) 0001 adc1 (p1.1) 0010 adc2 (p1.2) 0011 adc3 (p1.3) 0100 adc4 (p1.4) 0101 connected with gnd internally . . . . . . 1110 connected with gnd internally 1111 connected with av ref internally note: maximum adc clock input = 2.5 mhz conversion speed selection bit: (note) 00 = fosc/16 (f osc < 16 mhz) 01 = fosc/8 (f osc < 16 mhz) 10 = fosc/4 (f osc < 10 mhz) 11 = fosc/1 (f osc < 2.5 mhz) = = = = figure 12- 1. a/d converter control register (adcon)
s3c9432/c9434/p9434 a/d converter 12- 3 internal reference voltage levels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must remain within the range av ss to av ref (usually, av ref = v dd ). different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first bit conversion is always 1/2 av ref . a/d converter control register adcon (f7h) m u l t i p l e x e r adcon .7-4 + _ control circuit successive approximation circuit clock selector d/a converter av ref av ss addatah (f8h) addatal (f9h) adcon .0 (aden) adcon .2-1 adcon .3 (eoc flag) analog comparator conversion result to data bus adc0/p1.0 adc1/p1.1 adc3/p1.3 adc2/p1.2 adc4/p1.4 figure 1 2- 2. a/d converter circuit diagram .9 .8 .7 .6 .5 .4 .3 .2 lsb msb - - - - - - .1 .0 lsb msb addatah addatal figure 1 2-3 . a/d converter data register (addatah/l)
a/d converter ks86c4302/c4304/p4 304 12- 4 50 adc clock conversion start eoc addata adcon.0 <- 1 9 8 7 6 5 4 3 2 1 0 previous value valid data set up time 10 clock 40 clock addatah (8-bit) + addatal (2-bit) figure 1 2-4 . a/d converter timing diagram conversion timing the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up a/d conversion. therefore, total of 50 clocks are required to complete an 10-bit conversion: with an 10 mhz cpu clock frequency, one clock cycle is 400 ns (4/fosc). if each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 10-bits + step-up time (10 clock) = 50 clocks 50 clock x 400 ns = 20 m s at 10 mhz, 1 clock time = 4/fosc (assuming adcon.2?.1 = 10) internal a/d conversion procedure 1. analog input must remain be tween the voltage range of av ss and av ref . 2. configure the analog input pins to input mode by mak ing the appropriate settings in p1conh and p 1 conl registers. 3. before the conversion operation starts, you must first select one of the five input pins (adc0 -adc4 ) by writing the appropriate value to the adcon register. 4. when conversion has been completed, (50 clocks have elapsed ), the eoc flag is set to ?1?, so that a check can be made to verify that the conversion was successful. 5 . t he converted digital value is loaded to the output register, addata h (8-bit) and addatal (2-bit) , then the adc module enters an idle state. 6. the digital conversion result can now be read from the addata h and addatal register.
ks86c4302/c4304/p4304 a/d converter 12- 5 notes: 1. the symbol 'r' signifies an offset resistor with a value of from 50 to 100 ohms. 2. it is recommended that gnd of the oscillator and gnd of the av ss /v ss must be connected separately with gnd of the power. v ss s3c9432 /c9434 av ss adc0-adc4 av ref reference voltage input analog input pin r 104 101 x in x out v dd v dd figure 1 2-5 . recommended a/d converter circuit for highest absolute accuracy
a/d converter ks86c4302/c4304/p4 304 12- 6 + + programming tip ? configuring a/d converter org 0000h vector 00h,int_4304 ; s3c9434 has only one interrupt vector org 0100h reset: di ; disable interrupt ld btcon,#10100011b ; watch-dog d isable ld p1conh,#00000011b ; configure p1.4 ad input ld p1conl,#11111111b ; configure p1.0-1.3 ad input ei ; enable interrupt ;--------------<< main loop >> main: call ad_conv ; subroutine for ad conversion jr t,main ; ad_conv: ld adcon,#00000001b ; select analog input channel --> p1.0 ; select conversion speed --> fosc/16 ; set coversion start bit conv_loop: tm adcon,#00001000b ; check eoc flag jr z,conv_loop ; if eoc flag=0, jump to conv_loop unti l eoc flag=1 ld r0,addatah ; high 8 bits of conversion result are stored ; to addatah register ld r1,addatal ; low 2 bits of conversion result are stored ; to addatal register ret ; int_4304: ; interrupt enable bit and pending bit check ; ; pending bit clear iret ; end
s3c9432/c9434/p9434 serial i/o interface 1 3- 1 13 serial i/o interface overview serial i/o module , sio can interface with various types of external devices that require serial data transfer. the components of each sio function block are: ? 8 -bit control register (siocon) ? clock selection logic ? 8-bit data buffer (siodata) ? 8 -bit prescaler (siops) ? 3-bit serial clock counter ? serial data i/o pins (si, so) ? external clock input pin (sck) sio module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. to ensure flexible data transmission rates, you can select an internal or external clock source. programming procedure to program the sio module, follow these basic steps: 1. configur e the i/o pins at port 3 (so, sck , si ) by loading the appropriate value to the p 1 con l and p2con register if necessary . 2 . load an 8-bit value to the siocon control register to properly configure the serial i/o module. in this operation, siocon.2 must be set to "1" to enable the data shifter. 3 . for interrupt generation, set the serial i/o interrupt enable bit (siocon. 1 ) to "1". 4 . when you the transmit data to the serial buffer, write data to siodata and set siocon.3 to 1, the shift operation starts. 5 . whe n the shift operation (transmit/receive) is completed, the sio pending bit (siocon. 0 ) is set to "1" and an sio interrupt request is generated.
serial i/o interface s3c9432/c9434/p9434 1 3- 2 serial i/o control registers (siocon) the control registers for serial i/o interface, siocon, is located at f0 h . it has the control settings for sio module. ? clock source selection (internal or external) for shift clock ? interrupt enable ? edge selection for shift operation ? clear 3-bit counte r and start shift operation ? shift operation (transmit) enable ? mode selection (transmit/receive or receive-only) ? data direction selection (msb first or lsb first) a reset clears the siocon value to "0 0h " . this configures the corresponding module with an internal clock source at the sck, selects receive-only operating mode, and clears the 3-bit counter. the data shift operation and the interrupt are disabled. the selected data direction is msb-first. lsb msb sio control register (siocon) f0h,r/w, reset: 00h siointerrupt enable bit: 0 = disable sio interrupt 1 = enable sio interrupt sio interrupt pending bit: 0 = no interrupt pending 0 = clear pending condition (when write) 1 = interrupt is pending .7 .6 .5 .4 .3 .2 .1 .0 sio shift clock select bit: 0 = internal clock (p.s clock) 1 = external clock (sck) data direction control bit: 0 = msb-first mode 1 = lsb-first mode sio counter clear and shift start bit: 0 = no action 1 = clear 3-bit counter and start shifting sio shift operation enable bit: 0 = disable shifter and clock counter 1 = enable shfter and clock counter sio mode selction bit: 0 = rececive-only mode 1 = transmit/receive mode shift clock edge selction bit: 0 = tx falling edges, rx at rising edges 1 = tx rising edges, rx at falling edges figure 13- 1. serial i/o interface control register (siocon)
s3c9432/c9434/p9434 serial i/o interface 1 3- 3 sio prescaler register (siops) the control register for serial i/o interface module, siops is located at f1h. the value stored in the sio prescaler registers, siops, lets you determine the sio clock rate (baud rate) as follows: baud rate = input clock(xin/2) / 2(pre-scaler value + 1), or external sck input clock lsb msb sio pre-scaler register (siops) f1h, r/w .7 .6 .5 .4 .3 .2 .1 .0 baud rate = (x in /4)/(siops + 1) figure 13-2. sio pre-scaler register (siops) sio int pending 3-bit counter siocon.0 mux 8-bit sio shift buffer (siodata) 8-bit prescaler 1/2 x in /2 siops (f1h) sck siocon.7 (shift clock source select) prescaler value =1/(siops + 1) clear clk siocon.1 (interrupt enable) clk si siocon.3 siocon.4 (edge select) siocon.5 (mode select) siocon.2 (shift enable) siocon.6 (lsb/msb first mode select) data bus 8 so toggle figure 13-3 . sio functional block diagram
serial i/o interface s3c9432/c9434/p9434 1 3- 4 so transmit complete irq0 set siocon.3 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 si sck figure 13-4 . serial i/o timing in transmit-receive mode (tx at falling, siocon.4 = 0) irq0 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck transmit complete set siocon.3 si so figure 13-5. serial i/o timing in transmit-receive mode (tx at rising, siocon.4 = 1) receive complete irq0 d7 d6 d5 d4 d3 d2 d1 d0 sck high impedance si so set siocon.3 figure 13-6 . serial i/o timing in receive-only mode
s3c9432/c9434/p9434 serial i/o interface 1 3- 5 + + programming tip ? sio org 0000h vector 00h,int_4304 ; s3c9434 has only one interrupt vector sio_rx_buf equ 40h sio_tx_buf equ 41h ;--------------<< initialize system and peripherals >> org 0100h reset: di ; disable interrupt ld btcon,#10100011b ; watch-dog disable ld p2con,#00000101b ; configure so (p2.1), sck (p2.0) ld p1conl,#00100000b ; configure si (p1.1) ld siocon,#00100110b ; enable sio, transmit/receive mode ld siops,#9 ; baud rate = (input clock)/40 ei ; enable interrupt ;--------------<< main loop >> main: call sio_mode ; to transmit data jr t,main ; ;--------------<< subroutine >> sio_mode: ld siodata,sio_tx_buf ; load transmission data or siocon,#00001000b ; after data loading siocon.3 bit must be set ret ;
serial i/o interface s3c9432/c9434/p9434 1 3- 6 + + programming tip ? sio (continued) ;--------------<< interrupt service routines >> int_4304: ; interrupt enable bit and pending bit check tm siocon,#00000010b ; interrupt enable bit check jr z,next_chk1 ; tm siocon,#00000001b ; interrupt pending bit check jp nz,int_sio ; sio interruopt next_chk1: iret ; int_sio: ; sio interrupt service routine ld sio_rx_buf,siodata ; save received data and siocon,#11110110b ; pending bit clear iret ; interrupt return end ;
s3c9432/c9434/p9434 electrical data 1 4- 1 1 4 electrical data overview in this section, the following s3c9432/c9434 electrical characteristics are presented in tables and graphs: ? absolute maximum ratings ? d.c. electrical characteristics ? a.c. electrical characteristics ? input timing measurement points ? oscillator characteristics ? oscillation stabilization time ? operating voltage range ? schmitt trigger input characteristics ? data retention supply voltage in stop mode ? stop mode release timing when initiated by a reset ? a/d converter electrical characteristics ? lvd circuit characteristics ? lvd reset timing ? serial i/o timing characteristics ? serial data transfer timing
electrical data s3c9432/c9434/p943 4 1 4- 2 table 14- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? - 0.3 to + 6.5 v input voltage v i all input ports - 0.3 to v dd + 0.3 v output v oltage v o all output ports - 0.3 to v dd + 0.3 v output c urrent high i oh one i/o pin active - 25 ma all i/o pins active - 80 output current l ow i ol one i/o pin active + 30 ma all i/o pins active + 1 5 0 operating temperature t a ? - 40 to + 85 c storage temperature t stg ? - 65 to + 150 c table 14- 2. dc electrical characteristics (t a = ? 4 0 c to + 85 c, v dd = 3.0 v to 5.5 v) parameter symbol conditions min typ max unit input high v oltage v i h1 ports 0, 1, and reset v dd = 3.0 to 5.5 v 0. 8 v dd ? v dd v v i h2 x in and x out v dd - 0.1 input low v oltage v i l1 ports 0, 1, and reset v dd = 3.0 to 5.5 v ? ? 0.2 v dd v v i l2 x in and x out 0.1 out put high v oltage v oh i oh = - 1 0 m a ports 0, 1, 2 v dd = 4.5 to 5.5 v v dd - 1. 5 v dd - 0.4 ? v output low v oltage v o l i o l = 25 m a port 0, 1, and 2 v dd = 4. 5 to 5.5 v ? 0.4 2.0 v
s3c9432/c9434/p9434 electrical data 1 4- 3 table 14- 2. dc electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v) parameter symbol conditions min typ max unit input h igh l eakage current i lih1 all input s except i lih2 v in = v dd ? ? 1 ua i lih2 x in , x out v in = v dd 20 input l ow l eakage current i lil1 all inputs except i lil2 and reset v in = 0 v ? ? - 1 ua i lil2 x in , x out v in = 0 v - 20 output h igh l eakage c urrent i loh all outputs v out = v dd ? ? 2 ua output l ow l eakage c urrent i lol all outputs v out = 0 v ? ? - 2 ua pull-up r esistors r p v in = 0 v ports 0 -2 v dd = 5 v 30 47 70 k w reset v dd = 5 v 100 200 350 supply c urren t i dd1 run mode 16 mhz cpu clock v dd = 5v 10% ? 11 20 ma 8 mhz cpu clock v dd = 3.3 v 3 6 i dd2 idle mode 1 6 mhz cpu clock v dd = 5v 10% ? 5 8 8 mhz cpu clock v dd = 3.3 v 0.7 2.5 i dd3 stop mode v dd = 5v 10% ? 65 100 ua v dd = 3.3 v 45 80 note: d.c electrical values for supply current (i dd , to i dd3 ) do not include current drawn through internal pull-up resisters, output port drive current and adc module.
electrical data s3c9432/c9434/p943 4 1 4- 4 table 14- 3. ac electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v) parameter symbol conditions min typ max unit interrupt input high, low width t inth , t intl int0, int1 v dd = 5v 10% ? 200 ? ns reset input l ow width t rsl input v dd = 5v 10% ? 1 ? us 0.8 v dd 0.2 v dd t intl t inth t rsl figure 14-1 . input timing measurement points
s3c9432/c9434/p9434 electrical data 1 4- 5 table 14-4 . oscillator characteristics (t a = - 40 c to + 85 c) oscillator clock circuit test condition min typ max unit main crystal or ceramic x in c1 c2 x out v dd = 4. 5 to 5.5 v v dd = 3.0 to 4.5 v 1 1 ? ? 16 8 mhz external clock x in x out v dd = 4. 5 to 5.5 v v dd = 3.0 to 4.5 v 1 1 ? ? 16 8 rc oscillator x in x out r v dd = 5 v , r = 10 k w v dd = 3 v, r = 22 k w ? ? 4 2 ? ? table 14-5 . oscillation stabilization time (t a = - 40 c to + 85 c, v dd = 3.0 v to 5.5 v) oscillator test condition min typ max unit main crystal f osc > 1.0 mhz ? ? 20 ms main ceramic oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 10 external clock (main system) x in input high and low width (t xh , t xl ) 25 ? 500 ns oscillator stabilization t wait when released by a reset (1) ? 2 1 6 /f osc ? ms wait time t wait when released by an interrupt (2) ? ? ? notes : 1 . f osc is the oscillator frequency. 2 . the duration of the oscillator stabilization wait time, t wait , when it is released by an interrupt is dete r mined by the setting s in the basic timer control register, btcon.
electrical data s3c9432/c9434/p943 4 1 4- 6 cpu clock 16mhz 8mhz 4mhz 3mhz 2mhz 1mhz 1 2 3 4 5 6 7 2.7 5.5 supply voltage (v) figure 14-2 . operating voltage range 0.3 v dd a = 0.2 v dd b = 0.4 v dd c = 0.6 v dd d = 0.8 v dd v out a 0.7 v dd v dd v ss b c d v in figure 14-3 . schmitt trigger input characteristics diagram
s3c9432/c9434/p9434 electrical data 1 4- 7 table 14-6 . data retention supply voltage in stop mode (t a = ? 40 c to + 85 c , v dd = 3.0 v to 5.5 v ) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2.0 ? 5.5 v data retention supply current i dddr stop mode; v dddr = 2.0 v ? 0.1 5 ua note: supply current does not include current drawn through internal pull-up resistors or external output current loads. reset data retention mode ~ ~ ~ v dddr execution of stop instrction v dd normal operating mode oscillation stabilization time ~ stop mode reset occurs t wait note: t wait is the same as 4096 x 16 x 1/fosc 0.8 v dd 0.2 v dd figure 14-4 . stop mode release timing when initiated by a reset reset
electrical data s3c9432/c9434/p943 4 1 4- 8 table 14-7. a/d converter electrical characteristics (t a = - 40 c to + 85 c , v dd = 3.0 v to 5.5 v, v ss = 0 v ) parameter symbol test conditions min typ max unit total accuracy ? v dd = 5.12 v cpu clock = 10 mhz av ref = 5.12 v av ss = 0 v ? ? 3 lsb integral linearity error ile ? ? ? 2 differential linearity error dle ? ? ? 1 offset error of top eot ? ? 1 3 offset error of bottom eob ? ? 1 2 conversion time (1) t con f osc = 10 mhz ? 50x4/ f osc ? m s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 ? ? m w adc reference voltage av ref ? 3.0 ? v dd v adc reference ground av ss ? v ss ? v ss + 0.3 v analog input current i adin av ref = v dd = 5 v ? ? 10 m a analog block current (2) i adc av ref = v dd = 5 v conversion time = 20 m s 1 3 ma av ref = v dd = 3 v conversion time = 20 m s 0.5 1.5 ma av ref = v dd = 5 v when power down mode 100 500 na notes: 1. ?conversion time? is the time required from the moment a conversion operation starts until it ends. 2. i adc is operating current during a/d conversion.
s3c9432/c9434/p9434 electrical data 1 4- 9 table 14-8 . lvd circuit characteristics (t a = - 40 c to + 85 c , v dd = 3.0 v to 5.5v ) parameter symbol conditions min typ max unit power-on reset voltage high v dd h 3.0 5.5 v power-on reset voltage low v dd l 0 2.6 3.0 v power supply voltage rise time t r 10 (note) us power supply voltage off time t off 0.5 sec power-on reset circuit i dd p r v dd = 5 v 10 % 65 100 ua consumption current v dd = 3 v 45 80 ua note: oscillation stabilization time = 2 16 /fx (= 6.55 ms at fx = 10 mhz) v dd v ddh v ddl t off t r figure 14-5. lvd reset timing
electrical data s3c9432/c9434/p943 4 1 4- 10 table 14-9 . serial i/o timing characteristics (t a = ? 4 0 c to + 85 c, v dd = 3.0 v to 5.5 v) parameter symbol conditions min typ max unit sck cycle time t cky external sck source 1000 ? ? ns internal sck source 1000 sck high, low width t kh , t kl external sck source 500 ? ? internal sck source t kcy /2 ? 50 si setup time to sck low t sik external sck source 250 ? ? internal sck source 250 si hold time to sck high t ksi external sck source 400 ? ? internal sck source 400 output delay for sck to so t kso external sck source ? ? 300 internal sck source 250 note : " sck " means serial i/o clock frequency, " si " means serial data input, and " so " means serial data output. output data input sck t kh t kcy 0.8 v dd 0.2 v dd t kso t sik t ksi 0.8 v dd 0.2 v dd si so t kl figure 14-6 . serial data transfer timing
s3c9432/c9434/p9434 electrical data 1 4- 11 0.0 5.0 1.0 2.0 3.0 4.0 fx = 16 mhz v dd (v) fx = 10 mhz fx = 8 mhz 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 idd1 (ma) figure 14-7. i dd1 vs v dd
electrical data s3c9432/c9434/p943 4 1 4- 12 0.0 5.0 1.0 2.0 3.0 4.0 vol (v) 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 iol (ma) v dd = 4.5 v v dd = 5.5 v v dd = 5.0 v figure 14-8. i ol vs v ol
s3c9432/c9434/p9434 electrical data 1 4- 13 0.0 5.0 1.0 2.0 3.0 4.0 voh (v) -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 ioh (ma) v dd = 5.5 v v dd = 5.0 v v dd = 4.5 v figure 14-9. i oh vs v oh
s3c9432/c9434/p9434 mechanical data 1 5- 1 1 5 mechanical data overview the s3c9432/c9434 is available in a 20 -pin s dip package (samsung: 20 -dip- 3 00 a ) , a 20 -pin so p package (samsung: 20 - sop - 375), a 18 -pin dip package (samsung: 18 -dip- 3 00 a). package dimensions are shown in figure 1 5- 1 , 15-2, and 15-3 . note : dimensions are in millimeters. 26.80 max 26.40 0 .20 (1.77) 20-dip-300a 6.40 0 .20 #20 #1 0.46 0.10 1.52 0.10 #11 #10 0-15 0.25 + 0.10 - 0.05 7.62 2.54 0.51 min 3.30 0.30 3.25 0.20 5.08 max figure 1 5- 1. 20 -dip -300a package dimensions
mechanical data s3c9432/c9434/p9434 1 5- 2 note : dimensions are in millimeters. 20-sop-375 10.30 0 .30 #11 #20 #1 #10 13.14 max 12.74 0 .20 (0.66) 0-8 0.203 + 0.10 - 0.05 9.53 7.50 0.20 0.85 0.20 0.05 min 2.30 0.10 2.50 max 0.40 0.10 max + 0.10 - 0.05 1.27 figure 1 5-2 . 20 - sop-375 package dimensions
s3c9432/c9434/p9434 mechanical data 1 5- 3 note : dimensions are in millimeters. 23.35 max 22.95 0 .20 (1.32) 6.40 0 .20 #18 #1 #10 #9 0-15 0.25 + 0.10 - 0.05 7.62 2.54 0.51 min 3.30 0.30 3.25 0.20 5.08 max 18-dip-300a 0.46 0.10 1.52 0.10 figure 1 5-3 . 18- dip -300a package dimensions
mechanical data s3c9432/c9434/p9434 1 5- 4 19.80 (0.81) 6.40 #16 #1 #9 #8 0.25 7.62 2.54 1.50 0.46 0.38 3.25 3.30 5.08 figure 1 5-4 . 16- dip -300a package dimensions
s3c9432/c9434/p9434 S3P9434 otp 16- 1 16 S3P9434 otp overview the S3P9434 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c9432/c9434 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the S3P9434 is fully compatible with the s3c9432/c9434, in function, in d.c. electrical characteristics, and in pin configuration. because of its simple programming requirements, the S3P9434 is ideal for use as an evaluation chip for the s3c9432/c9434. v ss /v ss x in x out v pp / test p0.2/t0ck/int0 p0.1/pwm reset reset /reset p0.0/buz p2.0/sck p2.2 note: the bolds indicate an otp pin name. S3P9434 20-dip (top view) v dd/ v dd p0.3/int1/ sclk p1.0/adc0/ sdat p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/clo av ref p2.1/so p2.3 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 figure 16-1 . pin assignment diagram ( 20 -pin dip package)
S3P9434 otp s3c9432/ c9434/p9434 16- 2 S3P9434 20-sop (top view) v dd/ v dd p0.3/int1 / sclk p1.0/adc0 / sdat p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/clo av ref p2.1/so p2.3 20 19 18 17 16 15 14 13 12 11 v ss /v ss x in x out v pp /test p0.2/t0ck/int0 p0.1/pwm reset reset /reset p0.0/buz p2.0/sck p2.2 1 2 3 4 5 6 7 8 9 10 note: the bolds indicate an otp pin name. figure 1 6-2 . pin assignment diagram ( 20 -pin sop package)
s3c9432/c9434/p9434 S3P9434 otp 16- 3 s3c9432/c9434 18-dip (top view) v dd/ v dd p0.3/int1/ sclk p1.0/adc0/ sdat p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/clo av ref p2.1/so 18 17 16 15 14 13 12 11 10 v ss /v ss x in x out v pp /test p0.2/t0ck/int0 p0.1/pwm reset reset /reset p0.0/buz p2.0/sck 1 2 3 4 5 6 7 8 9 note: the bolds indicate an otp pin name. figure 1 6-3 . pin assignment diagram ( 18 -pin dip package)
S3P9434 otp s3c9432/ c9434/p9434 16- 4 S3P9434 16-dip (top view) v dd/ v dd p0.3/int1/ sclk p1.0/adc0/ sdat p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/clo av ref 16 15 14 13 12 11 10 9 v ss /v ss x in x out v pp /test p0.2/t0ck/int0 p0.1/pwm reset reset /reset p0.0/buz 1 2 3 4 5 6 7 8 note: the bolds indicate an otp pin name. figure 16-4. pin assingment diagram (16-pin dip package)
s3c9432/c9434/p9434 S3P9434 otp 16- 5 table 16-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p0.3 sdat 18 (20-pin) 16 (18-pin) i/o serial data pin (output when reading, input when writing) input and push-pull output port can be assigned p0.2 sclk 19 (20-pin) 17 (18-pin) i serial clock pin (input only pin) test v pp (test) 4 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 7 i chip initialization v dd /v ss v dd /v ss 20 (20-pin), 18 (18-pin) 1 (20-pin), 1 (18-pin) i logic power supply pin. note : ( ) means the sop otp pin number. table 16-2. comparison of S3P9434 and s3c9432/c9434 features characteristic S3P9434 s3c9432/c9434 program memory 4 kbyte eprom 2k/4k byte mask rom operating voltage (v dd ) 3.0 v to 5.5 v 3.0 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v pin configuration 20 dip/20 sop/18 dip eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the S3P9434, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-3 below. table 16-3. operating mode selection criteria v dd vpp (test) reg/ mem mem address (a15-a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
s3c9432/c9434/p9434 development tools 1 7- 1 1 7 development tools overview samsung provides a powerf u l and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7 , s3c8 , s3c9 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, a s sembler, and a program for setting options. shine samsung host interface for i n -circuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, hig hlighted, added, or removed compl etely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm86 the sasm86 is an relocatable assembler for samsung's s3c9 -series microcontrollers. the sasm86 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm86 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value " ff " is filled into the unused rom area upto the maximum rom size of the targe t device automatically.
development tools s3c9432/c9434/p943 4 1 7- 2 target boards target boards are available for all s3c9 -series microcontrollers. all required target system cables and adapters are included with the device-specific target board. otp s one times programmable microcontrollers (otps) are under development for s3c9432/c9434 microcontroller. bus smds2+ rs-232c pod probe adapter prom/otp writer unit ram break/display unit trace/timer unit sam8 base unit power supply unit ibm-pc at or compatible tb9432/9434 target board eva chip target application system figure 1 7-1 . smds product configuration (smds2+)
s3c9432/c9434/p9434 development tools 1 7- 3 tb9432/9434 target board the tb9432/9434 target board is used for the s3c9432/c9434 microcontroller s . it is supported by the smds2+ development systems. the tb9432/9434 target board can also be used for s3c9432/c9434 . 25 tb9432/9434 sm1323a to user_vcc off on 1 cn1 100-pin connector reset vcc gnd u1 + stop + idle 16 30-pin dip socket j101 15 1 30 80 qfp s3e9430 eva chip 24 1 smds2+ smds2 external triggers ch1 ch2 figure 1 7-2 . tb9432/9434 target board configuration
development tools s3c9432/c9434/p943 4 1 7- 4 table 1 7- 1. power selection settings for tb9432/9434 " to user_vcc " settings operating mode comments to user_vcc off on tb9432 /9434 target system v ss v cc smds2+ v cc external the smds2+ main board supplies v cc to the target board (evaluation chip) and the target system. on to user_vcc off external tb9432 /9434 target system vcc v ss v cc smds2+ the smds2+ main board supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. note: the following symbol in the " to user_vcc " setting column indicates the electrical short (off) configuration: smds2+ selection (sam8) in order to write data into program memory that is available in smds2+, the target board should be selected to be for smds2+ through a switch as follows. otherwise, the program memory writing function is not available. table 1 7-2 . the smds2+ tool selection setting "sw1" setting operating mode smds smds2+ smds2+ target board r/w r/w
s3c9432/c9434/p9434 development tools 1 7- 5 table 1 7-3 . using single header pins as the input path for external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) for the smds2+ breakpoint and trace functions.
development tools s3c9432/c9434/p943 4 1 7- 6 v ss n c nc test p0.2/t0ck/int0 p0.1/pwm reset p0.0/buz p2.0/sck p2.2 v dd p0.3/int1 p1.0/adc0 p1.1/adc1/si p1.2/adc2/so p 1.3/adc3/sck p1.4/adc4/clo av ref p2.1/so p2.3 j101 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 20-pin dip socket figure 1 7-3 . 2 0-pin connector for tb9432/9434 target system target board 20-pin connector j101 part name: ap20d order code: sm6304 1 20 10 11 1 20 10 11 20-pin connector figure 1 7-4 . s3c9432/c9434 probe adapter for 20-dip package

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